| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (C) 2016 PHYTEC Messtechnik GmbH |
| * Author: Christian Hemp <c.hemp@phytec.de> |
| */ |
| |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/pwm/pwm.h> |
| #include "imx6ul.dtsi" |
| |
| / { |
| model = "Phytec phyCORE i.MX6 UltraLite"; |
| compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul"; |
| |
| chosen { |
| stdout-path = &uart1; |
| }; |
| |
| /* |
| * Set the minimum memory size here and |
| * let the bootloader set the real size. |
| */ |
| memory { |
| device_type = "memory"; |
| reg = <0x80000000 0x8000000>; |
| }; |
| |
| gpio_leds_som: leds { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_gpioleds_som>; |
| compatible = "gpio-leds"; |
| |
| led_green { |
| label = "phycore:green"; |
| gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; |
| linux,default-trigger = "heartbeat"; |
| }; |
| }; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet1>; |
| phy-mode = "rmii"; |
| phy-handle = <ðphy0>; |
| status = "okay"; |
| |
| mdio: mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@1 { |
| reg = <1>; |
| interrupt-parent = <&gpio1>; |
| interrupts = <2 IRQ_TYPE_LEVEL_LOW>; |
| micrel,led-mode = <1>; |
| clocks = <&clks IMX6UL_CLK_ENET_REF>; |
| clock-names = "rmii-ref"; |
| }; |
| }; |
| }; |
| |
| &gpmi { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_gpmi_nand>; |
| nand-on-flash-bbt; |
| status = "okay"; |
| }; |
| |
| &i2c1 { |
| pinctrl-names = "default"; |
| pinctrl-0 =<&pinctrl_i2c1>; |
| clock-frequency = <100000>; |
| status = "okay"; |
| |
| eeprom@52 { |
| compatible = "catalyst,24c32", "atmel,24c32"; |
| reg = <0x52>; |
| }; |
| }; |
| |
| &snvs_poweroff { |
| status = "okay"; |
| }; |
| |
| &uart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl_enet1: enet1grp { |
| fsl,pins = < |
| MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 |
| MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 |
| MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 |
| MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 |
| MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 |
| MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 |
| MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 |
| MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 |
| MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 |
| MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 |
| MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x17059 |
| >; |
| }; |
| |
| pinctrl_gpioleds_som: gpioledssomgrp { |
| fsl,pins = <MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0>; |
| }; |
| |
| pinctrl_gpmi_nand: gpminandgrp { |
| fsl,pins = < |
| MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 |
| MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 |
| MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 |
| MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 |
| MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 |
| MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 |
| MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 |
| MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 |
| MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 |
| MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 |
| MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 |
| MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 |
| MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 |
| MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 |
| MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2cgrp { |
| fsl,pins = < |
| MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 |
| MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 |
| >; |
| }; |
| |
| pinctrl_uart1: uart1grp { |
| fsl,pins = < |
| MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 |
| MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 |
| >; |
| }; |
| |
| }; |
