)]}'
{
  "commit": "29f144016f03608abfddcd6ebaeabafd7aeaadd2",
  "tree": "3217e60164a7d19da7cc2374012f19ed57891176",
  "parents": [
    "3a82195416fd71fdd6cb4ff80f611ec28073be16"
  ],
  "author": {
    "name": "Seongjun Hong",
    "email": "hsj0512@snu.ac.kr",
    "time": "Tue Oct 06 14:16:45 2026 +0000"
  },
  "committer": {
    "name": "Paolo Abeni",
    "email": "pabeni@redhat.com",
    "time": "Mon Oct 12 16:30:21 2026 +0200"
  },
  "message": "net/mlx5: allocate DMA pool structs on the pool\u0027s NUMA node\n\nThe mlx5 DMA pool structs (mlx5_dma_pool, mlx5_dma_pool_page and its\nblock bitmap, and mlx5_frag_buf_node_pools) are allocated without a\nnode hint, so they land on the node of whichever CPU happens to create\nor fill the pool, while the DMA pages they describe are allocated on\nthe pool\u0027s node.\n\nThe pool, page and bitmap are dereferenced on every block allocation\nand free. Allocate them on the pool\u0027s NUMA node as well, so that all\nof a pool\u0027s state lives on one node.\n\nThese allocations happen on the control path, so the performance gain\nis expected to be small; the change is mainly for consistency.\n\nSigned-off-by: Seongjun Hong \u003chsj0512@snu.ac.kr\u003e\nReviewed-by: Jacob Keller \u003cjacob.e.keller@intel.com\u003e\nReviewed-by: Tariq Toukan \u003ctariqt@nvidia.com\u003e\nLink: https://patch.msgid.link/20261006-net-mlx5-numa-allocate-pool-page-v2-1-0dc4c2eb1376@snu.ac.kr\nSigned-off-by: Paolo Abeni \u003cpabeni@redhat.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a92cf545bdaf19df463b37cdf0f66d4b6867b23e",
      "old_mode": 33188,
      "old_path": "drivers/net/ethernet/mellanox/mlx5/core/alloc.c",
      "new_id": "dcd281c4691d7fbcca2dabd83f19e2728f7a5ab0",
      "new_mode": 33188,
      "new_path": "drivers/net/ethernet/mellanox/mlx5/core/alloc.c"
    }
  ]
}