commit 53eacc1fa688f066a5426f44fbc85710677fc172
author Palmer Dabbelt <palmer@rivosinc.com> Fri Apr 01 14:57:42 2022 -0700
committer Palmer Dabbelt <palmer@rivosinc.com> Fri Apr 01 22:04:33 2022 -0700
tree 8b72782789859f33d4a0e4082fb9115b34f7b136
parent 8210bae9ff34cc6fd0f3734957b8d20c8cb6166d

RISC-V: Add the Zifencei extension

Recent versions of binutils default to an ISA spec version that doesn't
include Zifencei as part of I, so Linux has recently started passing
this in -march.

Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

target-riscv.c

diff --git a/target-riscv.c b/target-riscv.c
index afd6faf..ff4dfba 100644
--- a/target-riscv.c
+++ b/target-riscv.c
@@ -18,6 +18,7 @@
 #define RISCV_FPU	(RISCV_FLOAT|RISCV_DOUBLE|RISCV_FDIV)
 #define RISCV_GENERIC	(RISCV_MUL|RISCV_DIV|RISCV_ATOMIC|RISCV_FPU)
 #define RISCV_ZICSR	(1 << 10)
+#define RISCV_ZIFENCEI	(1 << 11)
 
 static unsigned int riscv_flags;
 
@@ -39,6 +40,7 @@
 		{ "d",		RISCV_DOUBLE|RISCV_FDIV|RISCV_ZICSR },
 		{ "c",		RISCV_COMP },
 		{ "_zicsr",	RISCV_ZICSR },
+		{ "_zifencei",	RISCV_ZIFENCEI },
 	};
 	int i;
 
@@ -132,6 +134,8 @@
 		predefine("__riscv_muldiv", 1, "1");
 	if (riscv_flags & RISCV_ZICSR)
 		predefine("__riscv_zicsr", 1, "1");
+	if (riscv_flags & RISCV_ZIFENCEI)
+		predefine("__riscv_zifencei", 1, "1");
 
 	if (cmodel)
 		predefine_strong("__riscv_cmodel_%s", cmodel);