RISC-V: Add support for the zicbom extension
This was recently added to binutils and with any luck will soon be in
Linux, without it sparse will fail when trying to build new kernels on
systems with new toolchains.
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
diff --git a/target-riscv.c b/target-riscv.c
index 217ab7e..db0f7e5 100644
--- a/target-riscv.c
+++ b/target-riscv.c
@@ -19,6 +19,7 @@
#define RISCV_GENERIC (RISCV_MUL|RISCV_DIV|RISCV_ATOMIC|RISCV_FPU)
#define RISCV_ZICSR (1 << 10)
#define RISCV_ZIFENCEI (1 << 11)
+#define RISCV_ZICBOM (1 << 12)
static unsigned int riscv_flags;
@@ -41,6 +42,7 @@
{ "c", RISCV_COMP },
{ "_zicsr", RISCV_ZICSR },
{ "_zifencei", RISCV_ZIFENCEI },
+ { "_zicbom", RISCV_ZICBOM },
};
int i;
@@ -131,6 +133,8 @@
predefine("__riscv_zicsr", 1, "1");
if (riscv_flags & RISCV_ZIFENCEI)
predefine("__riscv_zifencei", 1, "1");
+ if (riscv_flags & RISCV_ZICBOM)
+ predefine("__riscv_zicbom", 1, "1");
if (cmodel)
predefine_strong("__riscv_cmodel_%s", cmodel);
