MIPS: Check Loongson3 LL/SC errata workaround correctness
When Loongson3 LL/SC errata workarounds are enabled (ie.
CONFIG_CPU_LOONGSON3_WORKAROUNDS=y) run a tool to scan through the
compiled kernel & ensure that the workaround is applied correctly. That
is, ensure that:
- Every LL or LLD instruction is preceded by a sync instruction.
- Any branches from within an LL/SC loop to outside of that loop
target a sync instruction.
Reasoning for these conditions can be found by reading the comment above
the definition of __SYNC_loongson3_war in arch/mips/include/asm/sync.h.
This tool will help ensure that we don't inadvertently introduce code
paths that miss the required workarounds.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Series-changes: 2
- Only try to build loongson3-llsc-check from arch/mips/Makefile when
CONFIG_CPU_LOONGSON3_WORKAROUNDS is enabled.
Series-version: 3
Series-to: linux-mips@vger.kernel.org
Series-cc: linux-kernel@vger.kernel.org
Series-cc: Huacai Chen <chenhc@lemote.com>
Series-cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cover-letter:
MIPS: barriers & atomics cleanups
This series consists of a bunch of cleanups to the way we handle memory
barriers (though no changes to the sync instructions we use to implement
them) & atomic memory accesses. One major goal was to ensure the
Loongson3 LL/SC errata workarounds are applied in a safe manner from
within inline-asm & that we can automatically verify the resulting
kernel binary looks reasonable. Many patches are cleanups found along
the way.
Applies atop v5.4-rc1.
Changes in v2:
- Keep our fls/ffs implementations. Turns out GCC's builtins call
intrinsics in some configurations, and if we'd need to go implement
those then using the generic fls/ffs doesn't seem like such a win.
- De-string __WEAK_LLSC_MB to allow use with __SYNC_ELSE().
- Only try to build the loongson3-llsc-check tool from
arch/mips/Makefile when CONFIG_CPU_LOONGSON3_WORKAROUNDS is enabled.
Changes in v3:
- Restore "\n" after __WEAK_LLSC_MB use in asm/futex.h.
END
5 files changed
