| /* |
| * Copyright 2013 Maxime Ripard |
| * |
| * Maxime Ripard <maxime.ripard@free-electrons.com> |
| * |
| * The code contained herein is licensed under the GNU General Public |
| * License. You may obtain a copy of the GNU General Public License |
| * Version 2 or later at the following locations: |
| * |
| * http://www.opensource.org/licenses/gpl-license.html |
| * http://www.gnu.org/copyleft/gpl.html |
| */ |
| |
| /include/ "skeleton.dtsi" |
| |
| / { |
| interrupt-parent = <&gic>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| compatible = "arm,cortex-a7"; |
| device_type = "cpu"; |
| reg = <0>; |
| }; |
| |
| cpu@1 { |
| compatible = "arm,cortex-a7"; |
| device_type = "cpu"; |
| reg = <1>; |
| }; |
| }; |
| |
| memory { |
| reg = <0x40000000 0x80000000>; |
| }; |
| |
| clocks { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| osc24M: osc24M@01c20050 { |
| #clock-cells = <0>; |
| compatible = "allwinner,sun4i-osc-clk"; |
| reg = <0x01c20050 0x4>; |
| clock-frequency = <24000000>; |
| }; |
| |
| osc32k: osc32k { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <32768>; |
| }; |
| |
| pll1: pll1@01c20000 { |
| #clock-cells = <0>; |
| compatible = "allwinner,sun4i-pll1-clk"; |
| reg = <0x01c20000 0x4>; |
| clocks = <&osc24M>; |
| }; |
| |
| /* |
| * This is a dummy clock, to be used as placeholder on |
| * other mux clocks when a specific parent clock is not |
| * yet implemented. It should be dropped when the driver |
| * is complete. |
| */ |
| pll6: pll6 { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <0>; |
| }; |
| |
| cpu: cpu@01c20054 { |
| #clock-cells = <0>; |
| compatible = "allwinner,sun4i-cpu-clk"; |
| reg = <0x01c20054 0x4>; |
| clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>; |
| }; |
| |
| axi: axi@01c20054 { |
| #clock-cells = <0>; |
| compatible = "allwinner,sun4i-axi-clk"; |
| reg = <0x01c20054 0x4>; |
| clocks = <&cpu>; |
| }; |
| |
| ahb: ahb@01c20054 { |
| #clock-cells = <0>; |
| compatible = "allwinner,sun4i-ahb-clk"; |
| reg = <0x01c20054 0x4>; |
| clocks = <&axi>; |
| }; |
| |
| ahb_gates: ahb_gates@01c20060 { |
| #clock-cells = <1>; |
| compatible = "allwinner,sun7i-a20-ahb-gates-clk"; |
| reg = <0x01c20060 0x8>; |
| clocks = <&ahb>; |
| clock-output-names = "ahb_usb0", "ahb_ehci0", |
| "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", |
| "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", |
| "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", |
| "ahb_nand", "ahb_sdram", "ahb_ace", |
| "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", |
| "ahb_spi2", "ahb_spi3", "ahb_sata", |
| "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", |
| "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", |
| "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", |
| "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", |
| "ahb_de_fe1", "ahb_gmac", "ahb_mp", |
| "ahb_mali"; |
| }; |
| |
| apb0: apb0@01c20054 { |
| #clock-cells = <0>; |
| compatible = "allwinner,sun4i-apb0-clk"; |
| reg = <0x01c20054 0x4>; |
| clocks = <&ahb>; |
| }; |
| |
| apb0_gates: apb0_gates@01c20068 { |
| #clock-cells = <1>; |
| compatible = "allwinner,sun7i-a20-apb0-gates-clk"; |
| reg = <0x01c20068 0x4>; |
| clocks = <&apb0>; |
| clock-output-names = "apb0_codec", "apb0_spdif", |
| "apb0_ac97", "apb0_iis0", "apb0_iis1", |
| "apb0_pio", "apb0_ir0", "apb0_ir1", |
| "apb0_iis2", "apb0_keypad"; |
| }; |
| |
| apb1_mux: apb1_mux@01c20058 { |
| #clock-cells = <0>; |
| compatible = "allwinner,sun4i-apb1-mux-clk"; |
| reg = <0x01c20058 0x4>; |
| clocks = <&osc24M>, <&pll6>, <&osc32k>; |
| }; |
| |
| apb1: apb1@01c20058 { |
| #clock-cells = <0>; |
| compatible = "allwinner,sun4i-apb1-clk"; |
| reg = <0x01c20058 0x4>; |
| clocks = <&apb1_mux>; |
| }; |
| |
| apb1_gates: apb1_gates@01c2006c { |
| #clock-cells = <1>; |
| compatible = "allwinner,sun7i-a20-apb1-gates-clk"; |
| reg = <0x01c2006c 0x4>; |
| clocks = <&apb1>; |
| clock-output-names = "apb1_i2c0", "apb1_i2c1", |
| "apb1_i2c2", "apb1_i2c3", "apb1_can", |
| "apb1_scr", "apb1_ps20", "apb1_ps21", |
| "apb1_i2c4", "apb1_uart0", "apb1_uart1", |
| "apb1_uart2", "apb1_uart3", "apb1_uart4", |
| "apb1_uart5", "apb1_uart6", "apb1_uart7"; |
| }; |
| }; |
| |
| soc@01c00000 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| emac: ethernet@01c0b000 { |
| compatible = "allwinner,sun4i-emac"; |
| reg = <0x01c0b000 0x1000>; |
| interrupts = <0 55 4>; |
| clocks = <&ahb_gates 17>; |
| status = "disabled"; |
| }; |
| |
| mdio@01c0b080 { |
| compatible = "allwinner,sun4i-mdio"; |
| reg = <0x01c0b080 0x14>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| pio: pinctrl@01c20800 { |
| compatible = "allwinner,sun7i-a20-pinctrl"; |
| reg = <0x01c20800 0x400>; |
| interrupts = <0 28 4>; |
| clocks = <&apb0_gates 5>; |
| gpio-controller; |
| interrupt-controller; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #gpio-cells = <3>; |
| |
| uart0_pins_a: uart0@0 { |
| allwinner,pins = "PB22", "PB23"; |
| allwinner,function = "uart0"; |
| allwinner,drive = <0>; |
| allwinner,pull = <0>; |
| }; |
| |
| uart6_pins_a: uart6@0 { |
| allwinner,pins = "PI12", "PI13"; |
| allwinner,function = "uart6"; |
| allwinner,drive = <0>; |
| allwinner,pull = <0>; |
| }; |
| |
| uart7_pins_a: uart7@0 { |
| allwinner,pins = "PI20", "PI21"; |
| allwinner,function = "uart7"; |
| allwinner,drive = <0>; |
| allwinner,pull = <0>; |
| }; |
| |
| i2c0_pins_a: i2c0@0 { |
| allwinner,pins = "PB0", "PB1"; |
| allwinner,function = "i2c0"; |
| allwinner,drive = <0>; |
| allwinner,pull = <0>; |
| }; |
| |
| i2c1_pins_a: i2c1@0 { |
| allwinner,pins = "PB18", "PB19"; |
| allwinner,function = "i2c1"; |
| allwinner,drive = <0>; |
| allwinner,pull = <0>; |
| }; |
| |
| i2c2_pins_a: i2c2@0 { |
| allwinner,pins = "PB20", "PB21"; |
| allwinner,function = "i2c2"; |
| allwinner,drive = <0>; |
| allwinner,pull = <0>; |
| }; |
| |
| emac_pins_a: emac0@0 { |
| allwinner,pins = "PA0", "PA1", "PA2", |
| "PA3", "PA4", "PA5", "PA6", |
| "PA7", "PA8", "PA9", "PA10", |
| "PA11", "PA12", "PA13", "PA14", |
| "PA15", "PA16"; |
| allwinner,function = "emac"; |
| allwinner,drive = <0>; |
| allwinner,pull = <0>; |
| }; |
| }; |
| |
| timer@01c20c00 { |
| compatible = "allwinner,sun4i-timer"; |
| reg = <0x01c20c00 0x90>; |
| interrupts = <0 22 4>, |
| <0 23 4>, |
| <0 24 4>, |
| <0 25 4>, |
| <0 67 4>, |
| <0 68 4>; |
| clocks = <&osc24M>; |
| }; |
| |
| wdt: watchdog@01c20c90 { |
| compatible = "allwinner,sun4i-wdt"; |
| reg = <0x01c20c90 0x10>; |
| }; |
| |
| sid: eeprom@01c23800 { |
| compatible = "allwinner,sun7i-a20-sid"; |
| reg = <0x01c23800 0x200>; |
| }; |
| |
| uart0: serial@01c28000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x01c28000 0x400>; |
| interrupts = <0 1 4>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&apb1_gates 16>; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@01c28400 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x01c28400 0x400>; |
| interrupts = <0 2 4>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&apb1_gates 17>; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@01c28800 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x01c28800 0x400>; |
| interrupts = <0 3 4>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&apb1_gates 18>; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@01c28c00 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x01c28c00 0x400>; |
| interrupts = <0 4 4>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&apb1_gates 19>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@01c29000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x01c29000 0x400>; |
| interrupts = <0 17 4>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&apb1_gates 20>; |
| status = "disabled"; |
| }; |
| |
| uart5: serial@01c29400 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x01c29400 0x400>; |
| interrupts = <0 18 4>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&apb1_gates 21>; |
| status = "disabled"; |
| }; |
| |
| uart6: serial@01c29800 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x01c29800 0x400>; |
| interrupts = <0 19 4>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&apb1_gates 22>; |
| status = "disabled"; |
| }; |
| |
| uart7: serial@01c29c00 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x01c29c00 0x400>; |
| interrupts = <0 20 4>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&apb1_gates 23>; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@01c2ac00 { |
| compatible = "allwinner,sun4i-i2c"; |
| reg = <0x01c2ac00 0x400>; |
| interrupts = <0 7 4>; |
| clocks = <&apb1_gates 0>; |
| clock-frequency = <100000>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@01c2b000 { |
| compatible = "allwinner,sun4i-i2c"; |
| reg = <0x01c2b000 0x400>; |
| interrupts = <0 8 4>; |
| clocks = <&apb1_gates 1>; |
| clock-frequency = <100000>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@01c2b400 { |
| compatible = "allwinner,sun4i-i2c"; |
| reg = <0x01c2b400 0x400>; |
| interrupts = <0 9 4>; |
| clocks = <&apb1_gates 2>; |
| clock-frequency = <100000>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@01c2b800 { |
| compatible = "allwinner,sun4i-i2c"; |
| reg = <0x01c2b800 0x400>; |
| interrupts = <0 88 4>; |
| clocks = <&apb1_gates 3>; |
| clock-frequency = <100000>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@01c2bc00 { |
| compatible = "allwinner,sun4i-i2c"; |
| reg = <0x01c2bc00 0x400>; |
| interrupts = <0 89 4>; |
| clocks = <&apb1_gates 15>; |
| clock-frequency = <100000>; |
| status = "disabled"; |
| }; |
| |
| gic: interrupt-controller@01c81000 { |
| compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; |
| reg = <0x01c81000 0x1000>, |
| <0x01c82000 0x1000>, |
| <0x01c84000 0x2000>, |
| <0x01c86000 0x2000>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupts = <1 9 0xf04>; |
| }; |
| }; |
| }; |
