| From cfcfae77ce69eab2372480b1d398e5e9671347bd Mon Sep 17 00:00:00 2001 |
| From: Simon Guinot <sguinot@lacie.com> |
| Date: Fri, 17 Sep 2010 23:33:51 +0200 |
| Subject: [PATCH] dmaengine: fix interrupt clearing for mv_xor |
| |
| commit cc60f8878eab892c03d06b10f389232b9b66bd83 upstream. |
| |
| When using simultaneously the two DMA channels on a same engine, some |
| transfers are never completed. For example, an endless lock can occur |
| while writing heavily on a RAID5 array (with async-tx offload support |
| enabled). |
| |
| Note that this issue can also be reproduced by using the DMA test |
| client. |
| |
| On a same engine, the interrupt cause register is shared between two |
| DMA channels. This patch make sure that the cause bit is only cleared |
| for the requested channel. |
| |
| Signed-off-by: Simon Guinot <sguinot@lacie.com> |
| Tested-by: Luc Saillard <luc@saillard.org> |
| Acked-by: saeed bishara <saeed.bishara@gmail.com> |
| Signed-off-by: Dan Williams <dan.j.williams@intel.com> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| --- |
| drivers/dma/mv_xor.c | 2 +- |
| 1 files changed, 1 insertions(+), 1 deletions(-) |
| |
| diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c |
| index e2fd34d..ba28b29 100644 |
| --- a/drivers/dma/mv_xor.c |
| +++ b/drivers/dma/mv_xor.c |
| @@ -162,7 +162,7 @@ static int mv_is_err_intr(u32 intr_cause) |
| |
| static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan) |
| { |
| - u32 val = (1 << (1 + (chan->idx * 16))); |
| + u32 val = ~(1 << (chan->idx * 16)); |
| dev_dbg(chan->device->common.dev, "%s, val 0x%08x\n", __func__, val); |
| __raw_writel(val, XOR_INTR_CAUSE(chan)); |
| } |
| -- |
| 1.7.0.4 |
| |
