| From 3d3c533f3b1b75d9070425be028763f39f738afc Mon Sep 17 00:00:00 2001 |
| From: Andreas Herrmann <andreas.herrmann3@amd.com> |
| Date: Thu, 30 Sep 2010 14:32:35 +0200 |
| Subject: [PATCH] x86, mtrr: Assume SYS_CFG[Tom2ForceMemTypeWB] exists on all future AMD CPUs |
| |
| commit 3fdbf004c1706480a7c7fac3c9d836fa6df20d7d upstream. |
| |
| Instead of adapting the CPU family check in amd_special_default_mtrr() |
| for each new CPU family assume that all new AMD CPUs support the |
| necessary bits in SYS_CFG MSR. |
| |
| Tom2Enabled is architectural (defined in APM Vol.2). |
| Tom2ForceMemTypeWB is defined in all BKDGs starting with K8 NPT. |
| In pre K8-NPT BKDG this bit is reserved (read as zero). |
| |
| W/o this adaption Linux would unnecessarily complain about bad MTRR |
| settings on every new AMD CPU family, e.g. |
| |
| [ 0.000000] WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 4863MB of RAM. |
| |
| Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> |
| LKML-Reference: <20100930123235.GB20545@loge.amd.com> |
| Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| --- |
| arch/x86/kernel/cpu/mtrr/cleanup.c | 2 +- |
| 1 files changed, 1 insertions(+), 1 deletions(-) |
| |
| diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/cleanup.c |
| index 06130b5..a670384 100644 |
| --- a/arch/x86/kernel/cpu/mtrr/cleanup.c |
| +++ b/arch/x86/kernel/cpu/mtrr/cleanup.c |
| @@ -827,7 +827,7 @@ int __init amd_special_default_mtrr(void) |
| |
| if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) |
| return 0; |
| - if (boot_cpu_data.x86 < 0xf || boot_cpu_data.x86 > 0x11) |
| + if (boot_cpu_data.x86 < 0xf) |
| return 0; |
| /* In case some hypervisor doesn't pass SYSCFG through: */ |
| if (rdmsr_safe(MSR_K8_SYSCFG, &l, &h) < 0) |
| -- |
| 1.7.0.4 |
| |
