| From foo@baz Wed Feb 7 19:38:23 CST 2018 |
| From: David Woodhouse <dwmw@amazon.co.uk> |
| Date: Thu, 25 Jan 2018 16:14:09 +0000 |
| Subject: x86/cpufeatures: Add CPUID_7_EDX CPUID leaf |
| |
| From: David Woodhouse <dwmw@amazon.co.uk> |
| |
| (cherry picked from commit 95ca0ee8636059ea2800dfbac9ecac6212d6b38f) |
| |
| This is a pure feature bits leaf. There are two AVX512 feature bits in it |
| already which were handled as scattered bits, and three more from this leaf |
| are going to be added for speculation control features. |
| |
| Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> |
| Signed-off-by: Thomas Gleixner <tglx@linutronix.de> |
| Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| Reviewed-by: Borislav Petkov <bp@suse.de> |
| Cc: gnomes@lxorguk.ukuu.org.uk |
| Cc: ak@linux.intel.com |
| Cc: ashok.raj@intel.com |
| Cc: dave.hansen@intel.com |
| Cc: karahmed@amazon.de |
| Cc: arjan@linux.intel.com |
| Cc: torvalds@linux-foundation.org |
| Cc: peterz@infradead.org |
| Cc: bp@alien8.de |
| Cc: pbonzini@redhat.com |
| Cc: tim.c.chen@linux.intel.com |
| Cc: gregkh@linux-foundation.org |
| Link: https://lkml.kernel.org/r/1516896855-7642-2-git-send-email-dwmw@amazon.co.uk |
| Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| arch/x86/include/asm/cpufeature.h | 7 +++++-- |
| arch/x86/include/asm/cpufeatures.h | 10 ++++++---- |
| arch/x86/include/asm/disabled-features.h | 3 ++- |
| arch/x86/include/asm/required-features.h | 3 ++- |
| arch/x86/kernel/cpu/common.c | 1 + |
| arch/x86/kernel/cpu/scattered.c | 2 -- |
| 6 files changed, 16 insertions(+), 10 deletions(-) |
| |
| --- a/arch/x86/include/asm/cpufeature.h |
| +++ b/arch/x86/include/asm/cpufeature.h |
| @@ -28,6 +28,7 @@ enum cpuid_leafs |
| CPUID_8000_000A_EDX, |
| CPUID_7_ECX, |
| CPUID_8000_0007_EBX, |
| + CPUID_7_EDX, |
| }; |
| |
| #ifdef CONFIG_X86_FEATURE_NAMES |
| @@ -78,8 +79,9 @@ extern const char * const x86_bug_flags[ |
| CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 15, feature_bit) || \ |
| CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 16, feature_bit) || \ |
| CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) || \ |
| + CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) || \ |
| REQUIRED_MASK_CHECK || \ |
| - BUILD_BUG_ON_ZERO(NCAPINTS != 18)) |
| + BUILD_BUG_ON_ZERO(NCAPINTS != 19)) |
| |
| #define DISABLED_MASK_BIT_SET(feature_bit) \ |
| ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \ |
| @@ -100,8 +102,9 @@ extern const char * const x86_bug_flags[ |
| CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 15, feature_bit) || \ |
| CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 16, feature_bit) || \ |
| CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) || \ |
| + CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) || \ |
| DISABLED_MASK_CHECK || \ |
| - BUILD_BUG_ON_ZERO(NCAPINTS != 18)) |
| + BUILD_BUG_ON_ZERO(NCAPINTS != 19)) |
| |
| #define cpu_has(c, bit) \ |
| (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ |
| --- a/arch/x86/include/asm/cpufeatures.h |
| +++ b/arch/x86/include/asm/cpufeatures.h |
| @@ -12,7 +12,7 @@ |
| /* |
| * Defines x86 CPU feature bits |
| */ |
| -#define NCAPINTS 18 /* N 32-bit words worth of info */ |
| +#define NCAPINTS 19 /* N 32-bit words worth of info */ |
| #define NBUGINTS 1 /* N 32-bit bug flags */ |
| |
| /* |
| @@ -197,9 +197,7 @@ |
| #define X86_FEATURE_RETPOLINE ( 7*32+12) /* Generic Retpoline mitigation for Spectre variant 2 */ |
| #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline mitigation for Spectre variant 2 */ |
| |
| -#define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */ |
| -#define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */ |
| -#define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ |
| +#define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ |
| |
| /* Because the ALTERNATIVE scheme is for members of the X86_FEATURE club... */ |
| #define X86_FEATURE_KAISER ( 7*32+31) /* CONFIG_PAGE_TABLE_ISOLATION w/o nokaiser */ |
| @@ -295,6 +293,10 @@ |
| #define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment and recovery */ |
| #define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */ |
| |
| +/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ |
| +#define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */ |
| +#define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */ |
| + |
| /* |
| * BUG word(s) |
| */ |
| --- a/arch/x86/include/asm/disabled-features.h |
| +++ b/arch/x86/include/asm/disabled-features.h |
| @@ -59,6 +59,7 @@ |
| #define DISABLED_MASK15 0 |
| #define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE) |
| #define DISABLED_MASK17 0 |
| -#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18) |
| +#define DISABLED_MASK18 0 |
| +#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19) |
| |
| #endif /* _ASM_X86_DISABLED_FEATURES_H */ |
| --- a/arch/x86/include/asm/required-features.h |
| +++ b/arch/x86/include/asm/required-features.h |
| @@ -100,6 +100,7 @@ |
| #define REQUIRED_MASK15 0 |
| #define REQUIRED_MASK16 0 |
| #define REQUIRED_MASK17 0 |
| -#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18) |
| +#define REQUIRED_MASK18 0 |
| +#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19) |
| |
| #endif /* _ASM_X86_REQUIRED_FEATURES_H */ |
| --- a/arch/x86/kernel/cpu/common.c |
| +++ b/arch/x86/kernel/cpu/common.c |
| @@ -737,6 +737,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c) |
| cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); |
| c->x86_capability[CPUID_7_0_EBX] = ebx; |
| c->x86_capability[CPUID_7_ECX] = ecx; |
| + c->x86_capability[CPUID_7_EDX] = edx; |
| } |
| |
| /* Extended state features: level 0x0000000d */ |
| --- a/arch/x86/kernel/cpu/scattered.c |
| +++ b/arch/x86/kernel/cpu/scattered.c |
| @@ -31,8 +31,6 @@ void init_scattered_cpuid_features(struc |
| const struct cpuid_bit *cb; |
| |
| static const struct cpuid_bit cpuid_bits[] = { |
| - { X86_FEATURE_AVX512_4VNNIW, CR_EDX, 2, 0x00000007, 0 }, |
| - { X86_FEATURE_AVX512_4FMAPS, CR_EDX, 3, 0x00000007, 0 }, |
| { X86_FEATURE_APERFMPERF, CR_ECX, 0, 0x00000006, 0 }, |
| { X86_FEATURE_EPB, CR_ECX, 3, 0x00000006, 0 }, |
| { X86_FEATURE_HW_PSTATE, CR_EDX, 7, 0x80000007, 0 }, |