| From ebcbeb0a11ceeba3478c530acca40626d2a7e342 Mon Sep 17 00:00:00 2001 |
| From: Helge Deller <deller@gmx.de> |
| Date: Mon, 26 Dec 2016 12:46:01 +0100 |
| Subject: [PATCH] parisc: Mark cr16 clocksource unstable on SMP systems |
| |
| commit 41744213602a206f24adcb4a2b7551db3c700e72 upstream. |
| |
| The cr16 interval timer of each CPU is not syncronized to other cr16 |
| timers in other CPUs in a SMP system. So, delay the registration of the |
| cr16 clocksource until all CPUs have been detected and then - if we are |
| on a SMP machine - mark the cr16 clocksource as unstable and lower it's |
| rating before registering it at the clocksource framework. |
| |
| This patch fixes the stalled CPU warnings which we have seen since |
| introduction of the cr16 clocksource. |
| |
| Signed-off-by: Helge Deller <deller@gmx.de> |
| Cc: <stable@vger.kernel.org> # v4.8+ |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/arch/parisc/kernel/time.c b/arch/parisc/kernel/time.c |
| index 325f30d82b64..47ef8fdcd382 100644 |
| --- a/arch/parisc/kernel/time.c |
| +++ b/arch/parisc/kernel/time.c |
| @@ -289,9 +289,26 @@ void __init time_init(void) |
| |
| cr16_hz = 100 * PAGE0->mem_10msec; /* Hz */ |
| |
| - /* register at clocksource framework */ |
| - clocksource_register_hz(&clocksource_cr16, cr16_hz); |
| - |
| /* register as sched_clock source */ |
| sched_clock_register(read_cr16_sched_clock, BITS_PER_LONG, cr16_hz); |
| } |
| + |
| +static int __init init_cr16_clocksource(void) |
| +{ |
| + /* |
| + * The cr16 interval timers are not syncronized across CPUs, so mark |
| + * them unstable and lower rating on SMP systems. |
| + */ |
| + if (num_online_cpus() > 1) { |
| + clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE; |
| + clocksource_cr16.rating = 0; |
| + } |
| + |
| + /* register at clocksource framework */ |
| + clocksource_register_hz(&clocksource_cr16, |
| + 100 * PAGE0->mem_10msec); |
| + |
| + return 0; |
| +} |
| + |
| +device_initcall(init_cr16_clocksource); |
| -- |
| 2.10.1 |
| |