blob: 0d92dc4ebd04833d93e0205d1066884ff45af788 [file] [log] [blame]
From 6e9d3924d4dd83254426f8ae6d978a395985be76 Mon Sep 17 00:00:00 2001
From: Fabrice Gasnier <>
Date: Wed, 18 Sep 2019 16:54:21 +0200
Subject: [PATCH] pwm: stm32-lp: Add check in case requested period cannot be
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commit c91e3234c6035baf5a79763cb4fcd5d23ce75c2b upstream.
LPTimer can use a 32KHz clock for counting. It depends on clock tree
configuration. In such a case, PWM output frequency range is limited.
Although unlikely, nothing prevents user from requesting a PWM frequency
above counting clock (32KHz for instance):
- This causes (prd - 1) = 0xffff to be written in ARR register later in
the apply() routine.
This results in badly configured PWM period (and also duty_cycle).
Add a check to report an error is such a case.
Signed-off-by: Fabrice Gasnier <>
Reviewed-by: Uwe Kleine-Kรถnig <>
Signed-off-by: Thierry Reding <>
Signed-off-by: Paul Gortmaker <>
diff --git a/drivers/pwm/pwm-stm32-lp.c b/drivers/pwm/pwm-stm32-lp.c
index 0059b24cfdc3..28e1f6413476 100644
--- a/drivers/pwm/pwm-stm32-lp.c
+++ b/drivers/pwm/pwm-stm32-lp.c
@@ -58,6 +58,12 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm,
/* Calculate the period and prescaler value */
div = (unsigned long long)clk_get_rate(priv->clk) * state->period;
do_div(div, NSEC_PER_SEC);
+ if (!div) {
+ /* Clock is too slow to achieve requested period. */
+ dev_dbg(priv->, "Can't reach %u ns\n", state->period);
+ return -EINVAL;
+ }
prd = div;
while (div > STM32_LPTIM_MAX_ARR) {