| From b24f816133f19e67f41b1c8d5fad5ebd12e17af3 Mon Sep 17 00:00:00 2001 |
| From: Lu Baolu <baolu.lu@linux.intel.com> |
| Date: Wed, 20 Nov 2019 14:10:16 +0800 |
| Subject: [PATCH] iommu/vt-d: Remove incorrect PSI capability check |
| |
| commit f81b846dcd9a1e6d120f73970a9a98b7fcaaffba upstream. |
| |
| The PSI (Page Selective Invalidation) bit in the capability register |
| is only valid for second-level translation. Intel IOMMU supporting |
| scalable mode must support page/address selective IOTLB invalidation |
| for first-level translation. Remove the PSI capability check in SVA |
| cache invalidation code. |
| |
| Fixes: 8744daf4b0699 ("iommu/vt-d: Remove global page flush support") |
| Cc: Jacob Pan <jacob.jun.pan@linux.intel.com> |
| Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> |
| Signed-off-by: Joerg Roedel <jroedel@suse.de> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c |
| index 641dc223c97b..12afcc0048f7 100644 |
| --- a/drivers/iommu/intel-svm.c |
| +++ b/drivers/iommu/intel-svm.c |
| @@ -104,11 +104,7 @@ static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_d |
| { |
| struct qi_desc desc; |
| |
| - /* |
| - * Do PASID granu IOTLB invalidation if page selective capability is |
| - * not available. |
| - */ |
| - if (pages == -1 || !cap_pgsel_inv(svm->iommu->cap)) { |
| + if (pages == -1) { |
| desc.qw0 = QI_EIOTLB_PASID(svm->pasid) | |
| QI_EIOTLB_DID(sdev->did) | |
| QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | |
| -- |
| 2.7.4 |
| |
