blob: 7f30a8614d00427edf4c579f046861fd11b14b44 [file] [log] [blame]
From c038a23b37e7e16e9a4bcb46e519b66c47bbbce8 Mon Sep 17 00:00:00 2001
From: Lubomir Rintel <>
Date: Wed, 18 Dec 2019 20:04:54 +0100
Subject: [PATCH] clk: mmp2: Fix the order of timer mux parents
commit 8bea5ac0fbc5b2103f8779ddff216122e3c2e1ad upstream.
Determined empirically, no documentation is available.
The OLPC XO-1.75 laptop used parent 1, that one being VCTCXO/4 (65MHz), but
thought it's a VCTCXO/2 (130MHz). The mmp2 timer driver, not knowing
what is going on, ended up just dividing the rate as of
commit f36797ee4380 ("ARM: mmp/mmp2: dt: enable the clock")'
Signed-off-by: Lubomir Rintel <>
Acked-by: Stephen Boyd <>
Signed-off-by: Olof Johansson <>
Signed-off-by: Paul Gortmaker <>
diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
index a60a1be937ad..b4a95cbbda98 100644
--- a/drivers/clk/mmp/clk-of-mmp2.c
+++ b/drivers/clk/mmp/clk-of-mmp2.c
@@ -134,7 +134,7 @@ static DEFINE_SPINLOCK(ssp3_lock);
static const char *ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
static DEFINE_SPINLOCK(timer_lock);
-static const char *timer_parent_names[] = {"clk32", "vctcxo_2", "vctcxo_4", "vctcxo"};
+static const char *timer_parent_names[] = {"clk32", "vctcxo_4", "vctcxo_2", "vctcxo"};
static DEFINE_SPINLOCK(reset_lock);