| From a943d477355b99a219472909e3d10ee5629143e3 Mon Sep 17 00:00:00 2001 |
| From: Samuel Holland <samuel@sholland.org> |
| Date: Sat, 28 Dec 2019 20:59:22 -0600 |
| Subject: [PATCH] clk: sunxi-ng: h6-r: Fix AR100/R_APB2 parent order |
| |
| commit 0c545240aebc2ccb8f661dc54283a14d64659804 upstream. |
| |
| According to the BSP source code, both the AR100 and R_APB2 clocks have |
| PLL_PERIPH0 as mux index 3, not 2 as it was on previous chips. The pre- |
| divider used for PLL_PERIPH0 should be changed to index 3 to match. |
| |
| This was verified by running a rough benchmark on the AR100 with various |
| clock settings: |
| |
| | mux | pre-divider | iterations/second | clock source | |
| |=====|=============|===================|==============| |
| | 0 | 0 | 19033 (stable) | osc24M | |
| | 2 | 5 | 11466 (unstable) | iosc/osc16M | |
| | 2 | 17 | 11422 (unstable) | iosc/osc16M | |
| | 3 | 5 | 85338 (stable) | pll-periph0 | |
| | 3 | 17 | 27167 (stable) | pll-periph0 | |
| |
| The relative performance numbers all match up (with pll-periph0 running |
| at its default 600MHz). |
| |
| Signed-off-by: Samuel Holland <samuel@sholland.org> |
| Signed-off-by: Maxime Ripard <maxime@cerno.tech> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c |
| index 27554eaf6929..3f78035ff85a 100644 |
| --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c |
| +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c |
| @@ -23,9 +23,9 @@ |
| */ |
| |
| static const char * const ar100_r_apb2_parents[] = { "osc24M", "osc32k", |
| - "pll-periph0", "iosc" }; |
| + "iosc", "pll-periph0" }; |
| static const struct ccu_mux_var_prediv ar100_r_apb2_predivs[] = { |
| - { .index = 2, .shift = 0, .width = 5 }, |
| + { .index = 3, .shift = 0, .width = 5 }, |
| }; |
| |
| static struct ccu_div ar100_clk = { |
| -- |
| 2.7.4 |
| |