| From b3d06c5c9ea5a053296212a52388eba4b96abbce Mon Sep 17 00:00:00 2001 |
| From: Hayes Wang <hayeswang@realtek.com> |
| Date: Wed, 22 Jan 2020 16:02:13 +0800 |
| Subject: [PATCH] r8152: disable DelayPhyPwrChg |
| |
| commit aa475d935272481c9ffb1ae54eeca5c1819fbe1a upstream. |
| |
| When enabling this, the device would wait an internal signal which |
| wouldn't be triggered. Then, the device couldn't enter P3 mode, so |
| the power consumption is increased. |
| |
| Signed-off-by: Hayes Wang <hayeswang@realtek.com> |
| Signed-off-by: David S. Miller <davem@davemloft.net> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c |
| index 881be35eba8d..8d193034c0f1 100644 |
| --- a/drivers/net/usb/r8152.c |
| +++ b/drivers/net/usb/r8152.c |
| @@ -28,7 +28,7 @@ |
| #define NETNEXT_VERSION "09" |
| |
| /* Information for net */ |
| -#define NET_VERSION "9" |
| +#define NET_VERSION "11" |
| |
| #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION |
| #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
| @@ -100,6 +100,7 @@ |
| #define PLA_BP_EN 0xfc38 |
| |
| #define USB_USB2PHY 0xb41e |
| +#define USB_SSPHYLINK1 0xb426 |
| #define USB_SSPHYLINK2 0xb428 |
| #define USB_U2P3_CTRL 0xb460 |
| #define USB_CSR_DUMMY1 0xb464 |
| @@ -350,6 +351,9 @@ |
| #define USB2PHY_SUSPEND 0x0001 |
| #define USB2PHY_L1 0x0002 |
| |
| +/* USB_SSPHYLINK1 */ |
| +#define DELAY_PHY_PWR_CHG BIT(1) |
| + |
| /* USB_SSPHYLINK2 */ |
| #define pwd_dn_scale_mask 0x3ffe |
| #define pwd_dn_scale(x) ((x) << 1) |
| @@ -3742,6 +3746,10 @@ static void rtl8153_up(struct r8152 *tp) |
| ocp_data &= ~LANWAKE_PIN; |
| ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data); |
| |
| + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1); |
| + ocp_data &= ~DELAY_PHY_PWR_CHG; |
| + ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data); |
| + |
| r8153_aldps_en(tp, true); |
| |
| switch (tp->version) { |
| -- |
| 2.7.4 |
| |
