| From b0bf97c9a39304eb6c2f31951fbbefdf7edfbcd3 Mon Sep 17 00:00:00 2001 |
| From: Icenowy Zheng <icenowy@aosc.io> |
| Date: Fri, 3 Jan 2020 22:35:03 -0800 |
| Subject: [PATCH] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock |
| |
| commit ec97faff743b398e21f74a54c81333f3390093aa upstream. |
| |
| The A64 PLL_CPU clock has the same instability if some factor changed |
| without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33, |
| H3. |
| |
| Add the mux and pll notifiers for A64 CPU clock to workaround the |
| problem. |
| |
| Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks") |
| Signed-off-by: Icenowy Zheng <icenowy@aosc.io> |
| Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> |
| Signed-off-by: Maxime Ripard <maxime@cerno.tech> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c |
| index 1786ee8fe8bb..d802ca251ca2 100644 |
| --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c |
| +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c |
| @@ -910,11 +910,26 @@ static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = { |
| .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets), |
| }; |
| |
| +static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = { |
| + .common = &pll_cpux_clk.common, |
| + /* copy from pll_cpux_clk */ |
| + .enable = BIT(31), |
| + .lock = BIT(28), |
| +}; |
| + |
| +static struct ccu_mux_nb sun50i_a64_cpu_nb = { |
| + .common = &cpux_clk.common, |
| + .cm = &cpux_clk.mux, |
| + .delay_us = 1, /* > 8 clock cycles at 24 MHz */ |
| + .bypass_index = 1, /* index of 24 MHz oscillator */ |
| +}; |
| + |
| static int sun50i_a64_ccu_probe(struct platform_device *pdev) |
| { |
| struct resource *res; |
| void __iomem *reg; |
| u32 val; |
| + int ret; |
| |
| res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| reg = devm_ioremap_resource(&pdev->dev, res); |
| @@ -928,7 +943,18 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev) |
| |
| writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); |
| |
| - return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc); |
| + ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc); |
| + if (ret) |
| + return ret; |
| + |
| + /* Gate then ungate PLL CPU after any rate changes */ |
| + ccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb); |
| + |
| + /* Reparent CPU during PLL CPU rate changes */ |
| + ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk, |
| + &sun50i_a64_cpu_nb); |
| + |
| + return 0; |
| } |
| |
| static const struct of_device_id sun50i_a64_ccu_ids[] = { |
| -- |
| 2.7.4 |
| |