| From 53ce14fbf2490428b237fadbd9e337dd180ab3b2 Mon Sep 17 00:00:00 2001 |
| From: Christophe Leroy <christophe.leroy@c-s.fr> |
| Date: Sun, 9 Feb 2020 18:14:42 +0000 |
| Subject: [PATCH] powerpc/8xx: Fix clearing of bits 20-23 in ITLB miss |
| |
| commit a4031afb9d10d97f4d0285844abbc0ab04245304 upstream. |
| |
| In ITLB miss handled the line supposed to clear bits 20-23 on the L2 |
| ITLB entry is buggy and does indeed nothing, leading to undefined |
| value which could allow execution when it shouldn't. |
| |
| Properly do the clearing with the relevant instruction. |
| |
| Fixes: 74fabcadfd43 ("powerpc/8xx: don't use r12/SPRN_SPRG_SCRATCH2 in TLB Miss handlers") |
| Cc: stable@vger.kernel.org # v5.0+ |
| Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> |
| Reviewed-by: Leonardo Bras <leonardo@linux.ibm.com> |
| Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> |
| Link: https://lore.kernel.org/r/4f70c2778163affce8508a210f65d140e84524b4.1581272050.git.christophe.leroy@c-s.fr |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S |
| index 5ab9178c2347..acd038b59dd3 100644 |
| --- a/arch/powerpc/kernel/head_8xx.S |
| +++ b/arch/powerpc/kernel/head_8xx.S |
| @@ -288,7 +288,7 @@ InstructionTLBMiss: |
| * set. All other Linux PTE bits control the behavior |
| * of the MMU. |
| */ |
| - rlwimi r10, r10, 0, 0x0f00 /* Clear bits 20-23 */ |
| + rlwinm r10, r10, 0, ~0x0f00 /* Clear bits 20-23 */ |
| rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */ |
| ori r10, r10, RPN_PATTERN | 0x200 /* Set 22 and 24-27 */ |
| mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ |
| -- |
| 2.7.4 |
| |
