| From eb5f0cc9c0feaf73daf15ef7c78b96334cfdccfa Mon Sep 17 00:00:00 2001 |
| From: Roger Quadros <rogerq@ti.com> |
| Date: Mon, 16 Mar 2020 12:27:31 +0200 |
| Subject: [PATCH] ARM: dts: omap5: Add bus_dma_limit for L3 bus |
| |
| commit dfa7ea303f56a3a8b1ed3b91ef35af2da67ca4ee upstream. |
| |
| The L3 interconnect's memory map is from 0x0 to |
| 0xffffffff. Out of this, System memory (SDRAM) can be |
| accessed from 0x80000000 to 0xffffffff (2GB) |
| |
| OMAP5 does support 4GB of SDRAM but upper 2GB can only be |
| accessed by the MPU subsystem. |
| |
| Add the dma-ranges property to reflect the physical address limit |
| of the L3 bus. |
| |
| Cc: stable@kernel.org |
| Signed-off-by: Roger Quadros <rogerq@ti.com> |
| Signed-off-by: Tony Lindgren <tony@atomide.com> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi |
| index edfd26c03462..d6cb07a822f5 100644 |
| --- a/arch/arm/boot/dts/omap5.dtsi |
| +++ b/arch/arm/boot/dts/omap5.dtsi |
| @@ -143,6 +143,7 @@ |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0xc0000000>; |
| + dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; |
| ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; |
| reg = <0 0x44000000 0 0x2000>, |
| <0 0x44800000 0 0x3000>, |
| -- |
| 2.7.4 |
| |
