| From 33dda53d4c3c3eab26cdc2816efa114ca25f7653 Mon Sep 17 00:00:00 2001 |
| From: Anson Huang <Anson.Huang@nxp.com> |
| Date: Wed, 11 Dec 2019 10:53:36 +0800 |
| Subject: [PATCH] ARM: imx: Enable ARM_ERRATA_814220 for i.MX6UL and i.MX7D |
| |
| commit 4562fa4c86c92a2df635fe0697c9e06379738741 upstream. |
| |
| ARM_ERRATA_814220 has below description: |
| |
| The v7 ARM states that all cache and branch predictor maintenance |
| operations that do not specify an address execute, relative to |
| each other, in program order. |
| However, because of this erratum, an L2 set/way cache maintenance |
| operation can overtake an L1 set/way cache maintenance operation. |
| This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, |
| r0p4, r0p5. |
| |
| i.MX6UL and i.MX7D have Cortex-A7 r0p5 inside, need to enable |
| ARM_ERRATA_814220 for proper workaround. |
| |
| Signed-off-by: Anson Huang <Anson.Huang@nxp.com> |
| Signed-off-by: Shawn Guo <shawnguo@kernel.org> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig |
| index 593bf1519608..4326c8f53462 100644 |
| --- a/arch/arm/mach-imx/Kconfig |
| +++ b/arch/arm/mach-imx/Kconfig |
| @@ -520,6 +520,7 @@ config SOC_IMX6UL |
| bool "i.MX6 UltraLite support" |
| select PINCTRL_IMX6UL |
| select SOC_IMX6 |
| + select ARM_ERRATA_814220 |
| |
| help |
| This enables support for Freescale i.MX6 UltraLite processor. |
| @@ -556,6 +557,7 @@ config SOC_IMX7D |
| select PINCTRL_IMX7D |
| select SOC_IMX7D_CA7 if ARCH_MULTI_V7 |
| select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M |
| + select ARM_ERRATA_814220 |
| help |
| This enables support for Freescale i.MX7 Dual processor. |
| |
| -- |
| 2.7.4 |
| |
