blob: def27f3136de6e70a551c41f2889567adf3a3029 [file] [log] [blame]
From 9b9abe371da531a7d52d4729510ef568ec4e6dbd Mon Sep 17 00:00:00 2001
From: Yicong Yang <>
Date: Fri, 13 Mar 2020 17:53:47 +0800
Subject: [PATCH] PCI/ASPM: Clear the correct bits when enabling L1 substates
commit 58a3862a10a317a81097ab0c78aecebabb1704f5 upstream.
In pcie_config_aspm_l1ss(), we cleared the wrong bits when enabling ASPM L1
Substates. Instead of the L1.x enable bits (PCI_L1SS_CTL1_L1SS_MASK, 0xf), we
cleared the Link Activation Interrupt Enable bit (PCI_L1SS_CAP_L1_PM_SS,
Clear the L1.x enable bits before writing the new L1.x configuration.
[bhelgaas: changelog]
Fixes: aeda9adebab8 ("PCI/ASPM: Configure L1 substate settings")
Signed-off-by: Yicong Yang <>
Signed-off-by: Bjorn Helgaas <>
CC: # v4.11+
Signed-off-by: Paul Gortmaker <>
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index fd4cb75088f9..535ee64da45e 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -743,9 +743,9 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
/* Enable what we need to enable */
pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
- PCI_L1SS_CAP_L1_PM_SS, val);
+ PCI_L1SS_CTL1_L1SS_MASK, val);
pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
- PCI_L1SS_CAP_L1_PM_SS, val);
+ PCI_L1SS_CTL1_L1SS_MASK, val);
static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)