blob: 45e755915d8872e9260a087f90b489ed6ca900b5 [file] [log] [blame]
From f9952408e9ffdf90656c0edcf1861a81581f154a Mon Sep 17 00:00:00 2001
From: Russell King <>
Date: Tue, 25 Feb 2020 11:45:12 +0000
Subject: [PATCH] arm64: dts: clearfog-gt-8k: set gigabit PHY reset deassert
commit 46f94c7818e7ab82758fca74935ef3d454340b4e upstream.
If the mv88e6xxx DSA driver is built as a module, it causes the
ethernet driver to re-probe when it's loaded. This in turn causes
the gigabit PHY to be momentarily reset and reprogrammed. However,
we attempt to reprogram the PHY immediately after deasserting reset,
and the PHY ignores the writes.
This results in the PHY operating in the wrong mode, and the copper
link states down.
Set a reset deassert delay of 10ms for the gigabit PHY to avoid this.
Fixes: babc5544c293 ("arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal")
Signed-off-by: Russell King <>
Acked-by: Baruch Siach <>
Signed-off-by: Gregory CLEMENT <>
Signed-off-by: Paul Gortmaker <>
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
index e4257bd9d1e9..e88efafbda39 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
@@ -364,6 +364,7 @@
pinctrl-0 = <&cp0_copper_eth_phy_reset>;
reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
switch0: switch0@4 {