| From 0cbb47defec80d482d9ce4166a9ca4f8b0d0c4e5 Mon Sep 17 00:00:00 2001 |
| From: Adrian Huang <ahuang12@lenovo.com> |
| Date: Fri, 14 Feb 2020 18:44:51 +0800 |
| Subject: [PATCH] iommu/amd: Fix the configuration of GCR3 table root pointer |
| |
| commit c20f36534666e37858a14e591114d93cc1be0d34 upstream. |
| |
| The SPA of the GCR3 table root pointer[51:31] masks 20 bits. However, |
| this requires 21 bits (Please see the AMD IOMMU specification). |
| This leads to the potential failure when the bit 51 of SPA of |
| the GCR3 table root pointer is 1'. |
| |
| Signed-off-by: Adrian Huang <ahuang12@lenovo.com> |
| Fixes: 52815b75682e2 ("iommu/amd: Add support for IOMMUv2 domain mode") |
| Signed-off-by: Joerg Roedel <jroedel@suse.de> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h |
| index 6db921d0450d..e8cb05dcb612 100644 |
| --- a/drivers/iommu/amd_iommu_types.h |
| +++ b/drivers/iommu/amd_iommu_types.h |
| @@ -341,7 +341,7 @@ |
| |
| #define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL) |
| #define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL) |
| -#define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0xfffffULL) |
| +#define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0x1fffffULL) |
| |
| #define DTE_GCR3_INDEX_A 0 |
| #define DTE_GCR3_INDEX_B 1 |
| -- |
| 2.7.4 |
| |
