| From f2e4e0c1b43d35b95a7bd0c479197b90ec04a889 Mon Sep 17 00:00:00 2001 |
| From: Julien Beraud <julien.beraud@orolia.com> |
| Date: Wed, 15 Apr 2020 14:24:31 +0200 |
| Subject: [PATCH] net: stmmac: fix enabling socfpga's ptp_ref_clock |
| |
| commit 15ce30609d1e88d42fb1cd948f453e6d5f188249 upstream. |
| |
| There are 2 registers to write to enable a ptp ref clock coming from the |
| fpga. |
| One that enables the usage of the clock from the fpga for emac0 and emac1 |
| as a ptp ref clock, and the other to allow signals from the fpga to reach |
| emac0 and emac1. |
| Currently, if the dwmac-socfpga has phymode set to PHY_INTERFACE_MODE_MII, |
| PHY_INTERFACE_MODE_GMII, or PHY_INTERFACE_MODE_SGMII, both registers will |
| be written and the ptp ref clock will be set as coming from the fpga. |
| Separate the 2 register writes to only enable signals from the fpga to |
| reach emac0 or emac1 when ptp ref clock is not coming from the fpga. |
| |
| Signed-off-by: Julien Beraud <julien.beraud@orolia.com> |
| Signed-off-by: David S. Miller <davem@davemloft.net> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c |
| index 29868557fc64..132e6317a3ba 100644 |
| --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c |
| +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c |
| @@ -266,16 +266,19 @@ static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac) |
| phymode == PHY_INTERFACE_MODE_MII || |
| phymode == PHY_INTERFACE_MODE_GMII || |
| phymode == PHY_INTERFACE_MODE_SGMII) { |
| - ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2); |
| regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG, |
| &module); |
| module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2)); |
| regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG, |
| module); |
| - } else { |
| - ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2)); |
| } |
| |
| + if (dwmac->f2h_ptp_ref_clk) |
| + ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2); |
| + else |
| + ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << |
| + (reg_shift / 2)); |
| + |
| regmap_write(sys_mgr_base_addr, reg_offset, ctrl); |
| |
| /* Deassert reset for the phy configuration to be sampled by |
| -- |
| 2.7.4 |
| |
