blob: 5ef12e1eaa48010cd57a9d1762cad0f69b204b55 [file] [log] [blame]
From e6abc9fa78377a4540e3c8a0c0e56a54a30da4fa Mon Sep 17 00:00:00 2001
From: Linus Walleij <>
Date: Sun, 15 Sep 2019 15:54:44 +0200
Subject: [PATCH] ARM: dts: dir685: Drop spi-cpol from the display
commit 2a7326caab479ca257c4b9bd67db42d1d49079bf upstream.
The D-Link DIR-685 had its clock polarity set as active
low using the special SPI "spi-cpol" property.
This is not correct: the datasheet clearly states:
"Fix SCL to GND level when not in use" which is
indicative that this line is active high.
After a recent fix making the GPIO-based SPI driver
force the clock line de-asserted at the beginning of
each SPI transaction this reared its ugly head: now
de-asserted was taken to mean the line should be
driven high, but it should be driven low.
Fix this up in the DTS file and the display works again.
Cc: Mark Brown <>
Fixes: 2922d1cc1696 ("spi: gpio: Add SPI_MASTER_GPIO_SS flag")
Signed-off-by: Linus Walleij <>
Signed-off-by: Arnd Bergmann <>
Signed-off-by: Paul Gortmaker <>
diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
index bfaa2de63a10..e2030ba16512 100644
--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts
+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
@@ -72,7 +72,6 @@
reg = <0>;
/* 50 ns min period = 20 MHz */
spi-max-frequency = <20000000>;
- spi-cpol; /* Clock active low */
vcc-supply = <&vdisp>;
iovcc-supply = <&vdisp>;
vci-supply = <&vdisp>;