| From 0728d23a7c954bb117d7cfe2306bc2bff65cf744 Mon Sep 17 00:00:00 2001 |
| From: Fabrizio Castro <fabrizio.castro@bp.renesas.com> |
| Date: Fri, 14 Jun 2019 12:53:32 +0100 |
| Subject: [PATCH] arm64: dts: renesas: r8a774a1: Add missing assigned-clocks |
| for CAN[01] |
| |
| commit 0a930f64a1cc36a34797a9e54f3040ad1d5833f2 upstream. |
| |
| Define "assigned-clocks" and "assigned-clock-rates" properties |
| for CAN[01] DT nodes, as required by the dt-bindings. |
| |
| Fixes: eccc40002972c424 ("arm64: dts: renesas: r8a774a1: Add clkp2 clock to CAN nodes") |
| Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> |
| Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi |
| index de282c4794ed..7180e51d389f 100644 |
| --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi |
| +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi |
| @@ -883,6 +883,8 @@ |
| <&cpg CPG_CORE R8A774A1_CLK_CANFD>, |
| <&can_clk>; |
| clock-names = "clkp1", "clkp2", "can_clk"; |
| + assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; |
| + assigned-clock-rates = <40000000>; |
| power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; |
| resets = <&cpg 916>; |
| status = "disabled"; |
| @@ -897,6 +899,8 @@ |
| <&cpg CPG_CORE R8A774A1_CLK_CANFD>, |
| <&can_clk>; |
| clock-names = "clkp1", "clkp2", "can_clk"; |
| + assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; |
| + assigned-clock-rates = <40000000>; |
| power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; |
| resets = <&cpg 915>; |
| status = "disabled"; |
| -- |
| 2.27.0 |
| |
