| From b8e3921f5975f97e61777aeda2ca1b1d320a93a7 Mon Sep 17 00:00:00 2001 |
| From: Robin Murphy <robin.murphy@arm.com> |
| Date: Mon, 30 Sep 2019 15:11:01 +0100 |
| Subject: [PATCH] iommu/io-pgtable-arm: Support all Mali configurations |
| |
| commit 1be08f458d1602275b02f5357ef069957058f3fd upstream. |
| |
| In principle, Midgard GPUs supporting smaller VA sizes should only |
| require 3-level pagetables, since level 0 only resolves bits 48:40 of |
| the address. However, the kbase driver does not appear to have any |
| notion of a variable start level, and empirically T720 and T820 rapidly |
| blow up with translation faults unless given a full 4-level table, |
| despite only supporting a 33-bit VA size. |
| |
| The 'real' IAS value is still valuable in terms of validating addresses |
| on map/unmap, so tweak the allocator to allow smaller values while still |
| forcing the resultant tables to the full 4 levels. As far as I can test, |
| this should make all known Midgard variants happy. |
| |
| Fixes: d08d42de6432 ("iommu: io-pgtable: Add ARM Mali midgard MMU page table format") |
| Tested-by: Neil Armstrong <narmstrong@baylibre.com> |
| Reviewed-by: Steven Price <steven.price@arm.com> |
| Reviewed-by: Rob Herring <robh@kernel.org> |
| Signed-off-by: Robin Murphy <robin.murphy@arm.com> |
| Signed-off-by: Will Deacon <will@kernel.org> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c |
| index 3310d9d9cb2e..1446c800a1dd 100644 |
| --- a/drivers/iommu/io-pgtable-arm.c |
| +++ b/drivers/iommu/io-pgtable-arm.c |
| @@ -1012,7 +1012,7 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie) |
| if (cfg->quirks) |
| return NULL; |
| |
| - if (cfg->ias != 48 || cfg->oas > 40) |
| + if (cfg->ias > 48 || cfg->oas > 40) |
| return NULL; |
| |
| cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G); |
| @@ -1021,6 +1021,11 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie) |
| if (!data) |
| return NULL; |
| |
| + /* Mali seems to need a full 4-level table regardless of IAS */ |
| + if (data->levels < ARM_LPAE_MAX_LEVELS) { |
| + data->levels = ARM_LPAE_MAX_LEVELS; |
| + data->pgd_size = sizeof(arm_lpae_iopte); |
| + } |
| /* |
| * MEMATTR: Mali has no actual notion of a non-cacheable type, so the |
| * best we can do is mimic the out-of-tree driver and hope that the |
| -- |
| 2.27.0 |
| |
