blob: 33d7d6ef4fcb3c15197c5432941b65ab2dedebe3 [file] [log] [blame]
From 76517254a274beb2799cc03fb3a8139194454ec8 Mon Sep 17 00:00:00 2001
From: Borislav Petkov <>
Date: Thu, 18 Jun 2020 20:25:25 +0200
Subject: [PATCH] EDAC/amd64: Read back the scrub rate PCI register on F15h
commit ee470bb25d0dcdf126f586ec0ae6dca66cb340a4 upstream.
da92110dfdfa ("EDAC, amd64_edac: Extend scrub rate support to F15hM60h")
added support for F15h, model 0x60 CPUs but in doing so, missed to read
back SCRCTRL PCI config register on F15h CPUs which are *not* model
0x60. Add that read so that doing
$ cat /sys/devices/system/edac/mc/mc0/sdram_scrub_rate
can show the previously set DRAM scrub rate.
Fixes: da92110dfdfa ("EDAC, amd64_edac: Extend scrub rate support to F15hM60h")
Reported-by: Anders Andersson <>
Signed-off-by: Borislav Petkov <>
Cc: <> #v4.4..
Signed-off-by: Paul Gortmaker <>
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 11a4dda00110..88a643aabcb0 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -265,6 +265,8 @@ static int get_scrub_rate(struct mem_ctl_info *mci)
if (pvt->model == 0x60)
amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval);
+ else
+ amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
case 0x17: