| From fa04495f484330596e29b32a5d1ddba8949b3788 Mon Sep 17 00:00:00 2001 |
| From: Doug Berger <opendmb@gmail.com> |
| Date: Thu, 31 Oct 2019 14:47:23 -0700 |
| Subject: [PATCH] arm64: apply ARM64_ERRATUM_845719 workaround for Brahma-B53 |
| core |
| |
| commit bfc97f9f199cb041cf897af3af096540948cc705 upstream. |
| |
| The Broadcom Brahma-B53 core is susceptible to the issue described by |
| ARM64_ERRATUM_845719 so this commit enables the workaround to be applied |
| when executing on that core. |
| |
| Since there are now multiple entries to match, we must convert the |
| existing ARM64_ERRATUM_845719 into an erratum list. |
| |
| Signed-off-by: Doug Berger <opendmb@gmail.com> |
| Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> |
| Signed-off-by: Will Deacon <will@kernel.org> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt |
| index bc80586f9593..d0e250bd677c 100644 |
| --- a/Documentation/arm64/silicon-errata.txt |
| +++ b/Documentation/arm64/silicon-errata.txt |
| @@ -65,6 +65,9 @@ stable kernels. |
| | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | |
| | ARM | MMU-500 | #841119,826419 | N/A | |
| | | | | | |
| +| Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_845719 | |
| ++----------------+-----------------+-----------------+-----------------------------+ |
| ++----------------+-----------------+-----------------+-----------------------------+ |
| | Cavium | ThunderX ITS | #22375,24313 | CAVIUM_ERRATUM_22375 | |
| | Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 | |
| | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | |
| diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h |
| index b1454d117cd2..aca07c2f6e6e 100644 |
| --- a/arch/arm64/include/asm/cputype.h |
| +++ b/arch/arm64/include/asm/cputype.h |
| @@ -79,6 +79,7 @@ |
| #define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3 |
| #define CAVIUM_CPU_PART_THUNDERX2 0x0AF |
| |
| +#define BRCM_CPU_PART_BRAHMA_B53 0x100 |
| #define BRCM_CPU_PART_VULCAN 0x516 |
| |
| #define QCOM_CPU_PART_FALKOR_V1 0x800 |
| @@ -105,6 +106,7 @@ |
| #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) |
| #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) |
| #define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2) |
| +#define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53) |
| #define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN) |
| #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) |
| #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR) |
| diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c |
| index 9a8b1b53d5fb..6d4b2802cf7e 100644 |
| --- a/arch/arm64/kernel/cpu_errata.c |
| +++ b/arch/arm64/kernel/cpu_errata.c |
| @@ -707,6 +707,16 @@ static const struct midr_range erratum_1418040_list[] = { |
| }; |
| #endif |
| |
| +#ifdef CONFIG_ARM64_ERRATUM_845719 |
| +static const struct midr_range erratum_845719_list[] = { |
| + /* Cortex-A53 r0p[01234] */ |
| + MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), |
| + /* Brahma-B53 r0p[0] */ |
| + MIDR_REV(MIDR_BRAHMA_B53, 0, 0), |
| + {}, |
| +}; |
| +#endif |
| + |
| const struct arm64_cpu_capabilities arm64_errata[] = { |
| #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE |
| { |
| @@ -747,10 +757,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = { |
| #endif |
| #ifdef CONFIG_ARM64_ERRATUM_845719 |
| { |
| - /* Cortex-A53 r0p[01234] */ |
| .desc = "ARM erratum 845719", |
| .capability = ARM64_WORKAROUND_845719, |
| - ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), |
| + ERRATA_MIDR_RANGE_LIST(erratum_845719_list), |
| }, |
| #endif |
| #ifdef CONFIG_CAVIUM_ERRATUM_23154 |
| -- |
| 2.7.4 |
| |
