| From 6a94dfa7a29a435828ce5cbed2108b153837dca2 Mon Sep 17 00:00:00 2001 |
| From: Yunhao Tian <t123yh@outlook.com> |
| Date: Wed, 13 Nov 2019 13:27:25 +0000 |
| Subject: [PATCH] drm/sun4i: tcon: Set min division of TCON0_DCLK to 1. |
| |
| commit 0b8e7bbde5e7e2c419567e1ee29587dae3b78ee3 upstream. |
| |
| The datasheet of V3s (and various other chips) wrote |
| that TCON0_DCLK_DIV can be >= 1 if only dclk is used, |
| and must >= 6 if dclk1 or dclk2 is used. As currently |
| neither dclk1 nor dclk2 is used (no writes to these |
| bits), let's set minimal division to 1. |
| |
| If this minimal division is 6, some common dot clock |
| frequencies can't be produced (e.g. 30MHz will not be |
| possible and will fallback to 25MHz), which is |
| obviously not an expected behaviour. |
| |
| Signed-off-by: Yunhao Tian <t123yh@outlook.com> |
| Signed-off-by: Maxime Ripard <maxime@cerno.tech> |
| Link: https://lore.kernel.org/linux-arm-kernel/MN2PR08MB57905AD8A00C08DA219377C989760@MN2PR08MB5790.namprd08.prod.outlook.com/ |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c |
| index 64c43ee6bd92..b597b3076c1d 100644 |
| --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c |
| +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c |
| @@ -485,7 +485,7 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, |
| |
| WARN_ON(!tcon->quirks->has_channel_0); |
| |
| - tcon->dclk_min_div = 6; |
| + tcon->dclk_min_div = 1; |
| tcon->dclk_max_div = 127; |
| sun4i_tcon0_mode_set_common(tcon, mode); |
| |
| -- |
| 2.7.4 |
| |
