| From f1fc62451b99402c27497e244404721e934d73f1 Mon Sep 17 00:00:00 2001 |
| From: Andrew Lunn <andrew@lunn.ch> |
| Date: Sat, 4 Jan 2020 23:14:51 +0100 |
| Subject: [PATCH] net: dsa: mv88e6xxx: Preserve priority when setting CPU port. |
| |
| commit d8dc2c9676e614ef62f54a155b50076888c8a29a upstream. |
| |
| The 6390 family uses an extended register to set the port connected to |
| the CPU. The lower 5 bits indicate the port, the upper three bits are |
| the priority of the frames as they pass through the switch, what |
| egress queue they should use, etc. Since frames being set to the CPU |
| are typically management frames, BPDU, IGMP, ARP, etc set the priority |
| to 7, the reset default, and the highest. |
| |
| Fixes: 33641994a676 ("net: dsa: mv88e6xxx: Monitor and Management tables") |
| Signed-off-by: Andrew Lunn <andrew@lunn.ch> |
| Tested-by: Chris Healy <cphealy@gmail.com> |
| Signed-off-by: David S. Miller <davem@davemloft.net> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/drivers/net/dsa/mv88e6xxx/global1.c b/drivers/net/dsa/mv88e6xxx/global1.c |
| index 09b8a3d0dd37..92efcf724d7e 100644 |
| --- a/drivers/net/dsa/mv88e6xxx/global1.c |
| +++ b/drivers/net/dsa/mv88e6xxx/global1.c |
| @@ -367,6 +367,11 @@ int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) |
| { |
| u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST; |
| |
| + /* Use the default high priority for management frames sent to |
| + * the CPU. |
| + */ |
| + port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI; |
| + |
| return mv88e6390_g1_monitor_write(chip, ptr, port); |
| } |
| |
| diff --git a/drivers/net/dsa/mv88e6xxx/global1.h b/drivers/net/dsa/mv88e6xxx/global1.h |
| index 7bd5ab733a3f..9b330c343aaa 100644 |
| --- a/drivers/net/dsa/mv88e6xxx/global1.h |
| +++ b/drivers/net/dsa/mv88e6xxx/global1.h |
| @@ -193,6 +193,7 @@ |
| #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST 0x2000 |
| #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST 0x2100 |
| #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST 0x3000 |
| +#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI 0x00e0 |
| #define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK 0x00ff |
| |
| /* Offset 0x1C: Global Control 2 */ |
| -- |
| 2.7.4 |
| |