| From 5f77d6ca5ca74e4b4a5e2e010f7ff50c45dea326 Mon Sep 17 00:00:00 2001 |
| From: Liu Yi L <yi.l.liu@intel.com> |
| Date: Fri, 24 Jul 2020 09:49:14 +0800 |
| Subject: [PATCH] iommu/vt-d: Enforce PASID devTLB field mask |
| |
| commit 5f77d6ca5ca74e4b4a5e2e010f7ff50c45dea326 upstream. |
| |
| Set proper masks to avoid invalid input spillover to reserved bits. |
| |
| Signed-off-by: Liu Yi L <yi.l.liu@intel.com> |
| Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> |
| Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> |
| Reviewed-by: Eric Auger <eric.auger@redhat.com> |
| Link: https://lore.kernel.org/r/20200724014925.15523-2-baolu.lu@linux.intel.com |
| Signed-off-by: Joerg Roedel <jroedel@suse.de> |
| |
| diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h |
| index 3e8fa1c7a1e6..311117b50e93 100644 |
| --- a/include/linux/intel-iommu.h |
| +++ b/include/linux/intel-iommu.h |
| @@ -381,8 +381,8 @@ enum { |
| |
| #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK) |
| #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11) |
| -#define QI_DEV_EIOTLB_GLOB(g) ((u64)g) |
| -#define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32) |
| +#define QI_DEV_EIOTLB_GLOB(g) ((u64)(g) & 0x1) |
| +#define QI_DEV_EIOTLB_PASID(p) ((u64)((p) & 0xfffff) << 32) |
| #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16) |
| #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4) |
| #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \ |
| -- |
| 2.27.0 |
| |
