| From 3386af51d3bcebcba3f7becdb1ef2e384abe90cf Mon Sep 17 00:00:00 2001 |
| From: Konrad Dybcio <konradybcio@gmail.com> |
| Date: Sun, 26 Jul 2020 13:12:05 +0200 |
| Subject: [PATCH] clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk |
| |
| commit 3386af51d3bcebcba3f7becdb1ef2e384abe90cf upstream. |
| |
| Add missing halt_check, hwcg_reg and hwcg_bit properties. |
| These were likely omitted when porting the driver upstream. |
| |
| Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> |
| Link: https://lore.kernel.org/r/20200726111215.22361-9-konradybcio@gmail.com |
| Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660") |
| Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
| |
| diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c |
| index a85283786278..f0b47b7d50ca 100644 |
| --- a/drivers/clk/qcom/gcc-sdm660.c |
| +++ b/drivers/clk/qcom/gcc-sdm660.c |
| @@ -1715,6 +1715,9 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = { |
| |
| static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = { |
| .halt_reg = 0x8a004, |
| + .halt_check = BRANCH_HALT, |
| + .hwcg_reg = 0x8a004, |
| + .hwcg_bit = 1, |
| .clkr = { |
| .enable_reg = 0x8a004, |
| .enable_mask = BIT(0), |
| -- |
| 2.27.0 |
| |
