| From e2269acee68d3bf29696ddb693e578db58240d5b Mon Sep 17 00:00:00 2001 |
| From: Yangyang Li <liyangyang20@huawei.com> |
| Date: Thu, 24 Oct 2019 17:21:57 +0800 |
| Subject: [PATCH] RDMA/hns: Bugfix for qpc/cqc timer configuration |
| |
| commit 887803db866a7a4e1817a3cb8a3eee4e9879fed2 upstream. |
| |
| qpc/cqc timer entry size needs one page, but currently they are fixedly |
| configured to 4096, which is not appropriate in 64K page scenarios. So |
| they should be modified to PAGE_SIZE. |
| |
| Fixes: 0e40dc2f70cd ("RDMA/hns: Add timer allocation support for hip08") |
| Link: https://lore.kernel.org/r/1571908917-16220-3-git-send-email-liweihang@hisilicon.com |
| Signed-off-by: Yangyang Li <liyangyang20@huawei.com> |
| Signed-off-by: Weihang Li <liweihang@hisilicon.com> |
| Signed-off-by: Jason Gunthorpe <jgg@mellanox.com> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h |
| index edfdbe2ce0db..4211a982a8e0 100644 |
| --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h |
| +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h |
| @@ -87,8 +87,8 @@ |
| #define HNS_ROCE_V2_MTT_ENTRY_SZ 64 |
| #define HNS_ROCE_V2_CQE_ENTRY_SIZE 32 |
| #define HNS_ROCE_V2_SCCC_ENTRY_SZ 32 |
| -#define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ 4096 |
| -#define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ 4096 |
| +#define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ PAGE_SIZE |
| +#define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ PAGE_SIZE |
| #define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFFF000 |
| #define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2 |
| #define HNS_ROCE_INVALID_LKEY 0x100 |
| -- |
| 2.7.4 |
| |
