)]}'
{
  "commit": "097e4311cda952dfb047f2a49d35aa5de500d474",
  "tree": "9dc6dff0a1c21956573c584478be689113e72e0c",
  "parents": [
    "b2d6504761a50b9493eb4b20f6e188b673f20c32"
  ],
  "author": {
    "name": "Like Xu",
    "email": "like.xu@linux.intel.com",
    "time": "Sat Jun 13 16:09:49 2020 +0800"
  },
  "committer": {
    "name": "Peter Zijlstra",
    "email": "peterz@infradead.org",
    "time": "Thu Jul 02 15:51:46 2020 +0200"
  },
  "message": "perf/x86: Add constraint to create guest LBR event without hw counter\n\nThe hypervisor may request the perf subsystem to schedule a time window\nto directly access the LBR records msrs for its own use. Normally, it would\ncreate a guest LBR event with callstack mode enabled, which is scheduled\nalong with other ordinary LBR events on the host but in an exclusive way.\n\nTo avoid wasting a counter for the guest LBR event, the perf tracks its\nhw-\u003eidx via INTEL_PMC_IDX_FIXED_VLBR and assigns it with a fake VLBR\ncounter with the help of new vlbr_constraint. As with the BTS event,\nthere is actually no hardware counter assigned for the guest LBR event.\n\nSigned-off-by: Like Xu \u003clike.xu@linux.intel.com\u003e\nSigned-off-by: Peter Zijlstra (Intel) \u003cpeterz@infradead.org\u003e\nLink: https://lkml.kernel.org/r/20200514083054.62538-5-like.xu@linux.intel.com\n",
  "tree_diff": [
    {
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      "old_path": "arch/x86/events/core.c",
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      "new_path": "arch/x86/events/core.c"
    },
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      "new_path": "arch/x86/events/intel/core.c"
    },
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      "old_mode": 33188,
      "old_path": "arch/x86/events/intel/lbr.c",
      "new_id": "d285d26c1578aab2b44aec213fed0574176b5432",
      "new_mode": 33188,
      "new_path": "arch/x86/events/intel/lbr.c"
    },
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      "old_path": "arch/x86/include/asm/perf_event.h",
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}