| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * SDM845 SoC device tree source |
| * |
| * Copyright (c) 2018, The Linux Foundation. All rights reserved. |
| */ |
| |
| #include <dt-bindings/clock/qcom,camcc-sdm845.h> |
| #include <dt-bindings/clock/qcom,dispcc-sdm845.h> |
| #include <dt-bindings/clock/qcom,gcc-sdm845.h> |
| #include <dt-bindings/clock/qcom,gpucc-sdm845.h> |
| #include <dt-bindings/clock/qcom,lpass-sdm845.h> |
| #include <dt-bindings/clock/qcom,rpmh.h> |
| #include <dt-bindings/clock/qcom,videocc-sdm845.h> |
| #include <dt-bindings/interconnect/qcom,osm-l3.h> |
| #include <dt-bindings/interconnect/qcom,sdm845.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/phy/phy-qcom-qusb2.h> |
| #include <dt-bindings/power/qcom-rpmpd.h> |
| #include <dt-bindings/reset/qcom,sdm845-aoss.h> |
| #include <dt-bindings/reset/qcom,sdm845-pdc.h> |
| #include <dt-bindings/soc/qcom,apr.h> |
| #include <dt-bindings/soc/qcom,rpmh-rsc.h> |
| #include <dt-bindings/clock/qcom,gcc-sdm845.h> |
| #include <dt-bindings/thermal/thermal.h> |
| |
| / { |
| interrupt-parent = <&intc>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| i2c0 = &i2c0; |
| i2c1 = &i2c1; |
| i2c2 = &i2c2; |
| i2c3 = &i2c3; |
| i2c4 = &i2c4; |
| i2c5 = &i2c5; |
| i2c6 = &i2c6; |
| i2c7 = &i2c7; |
| i2c8 = &i2c8; |
| i2c9 = &i2c9; |
| i2c10 = &i2c10; |
| i2c11 = &i2c11; |
| i2c12 = &i2c12; |
| i2c13 = &i2c13; |
| i2c14 = &i2c14; |
| i2c15 = &i2c15; |
| spi0 = &spi0; |
| spi1 = &spi1; |
| spi2 = &spi2; |
| spi3 = &spi3; |
| spi4 = &spi4; |
| spi5 = &spi5; |
| spi6 = &spi6; |
| spi7 = &spi7; |
| spi8 = &spi8; |
| spi9 = &spi9; |
| spi10 = &spi10; |
| spi11 = &spi11; |
| spi12 = &spi12; |
| spi13 = &spi13; |
| spi14 = &spi14; |
| spi15 = &spi15; |
| }; |
| |
| chosen { }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| /* We expect the bootloader to fill in the size */ |
| reg = <0 0x80000000 0 0>; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| hyp_mem: memory@85700000 { |
| reg = <0 0x85700000 0 0x600000>; |
| no-map; |
| }; |
| |
| xbl_mem: memory@85e00000 { |
| reg = <0 0x85e00000 0 0x100000>; |
| no-map; |
| }; |
| |
| aop_mem: memory@85fc0000 { |
| reg = <0 0x85fc0000 0 0x20000>; |
| no-map; |
| }; |
| |
| aop_cmd_db_mem: memory@85fe0000 { |
| compatible = "qcom,cmd-db"; |
| reg = <0x0 0x85fe0000 0 0x20000>; |
| no-map; |
| }; |
| |
| smem_mem: memory@86000000 { |
| reg = <0x0 0x86000000 0 0x200000>; |
| no-map; |
| }; |
| |
| tz_mem: memory@86200000 { |
| reg = <0 0x86200000 0 0x2d00000>; |
| no-map; |
| }; |
| |
| rmtfs_mem: memory@88f00000 { |
| compatible = "qcom,rmtfs-mem"; |
| reg = <0 0x88f00000 0 0x200000>; |
| no-map; |
| |
| qcom,client-id = <1>; |
| qcom,vmid = <15>; |
| }; |
| |
| qseecom_mem: memory@8ab00000 { |
| reg = <0 0x8ab00000 0 0x1400000>; |
| no-map; |
| }; |
| |
| camera_mem: memory@8bf00000 { |
| reg = <0 0x8bf00000 0 0x500000>; |
| no-map; |
| }; |
| |
| ipa_fw_mem: memory@8c400000 { |
| reg = <0 0x8c400000 0 0x10000>; |
| no-map; |
| }; |
| |
| ipa_gsi_mem: memory@8c410000 { |
| reg = <0 0x8c410000 0 0x5000>; |
| no-map; |
| }; |
| |
| gpu_mem: memory@8c415000 { |
| reg = <0 0x8c415000 0 0x2000>; |
| no-map; |
| }; |
| |
| adsp_mem: memory@8c500000 { |
| reg = <0 0x8c500000 0 0x1a00000>; |
| no-map; |
| }; |
| |
| wlan_msa_mem: memory@8df00000 { |
| reg = <0 0x8df00000 0 0x100000>; |
| no-map; |
| }; |
| |
| mpss_region: memory@8e000000 { |
| reg = <0 0x8e000000 0 0x7800000>; |
| no-map; |
| }; |
| |
| venus_mem: memory@95800000 { |
| reg = <0 0x95800000 0 0x500000>; |
| no-map; |
| }; |
| |
| cdsp_mem: memory@95d00000 { |
| reg = <0 0x95d00000 0 0x800000>; |
| no-map; |
| }; |
| |
| mba_region: memory@96500000 { |
| reg = <0 0x96500000 0 0x200000>; |
| no-map; |
| }; |
| |
| slpi_mem: memory@96700000 { |
| reg = <0 0x96700000 0 0x1400000>; |
| no-map; |
| }; |
| |
| spss_mem: memory@97b00000 { |
| reg = <0 0x97b00000 0 0x100000>; |
| no-map; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| CPU0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo385"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| cpu-idle-states = <&LITTLE_CPU_SLEEP_0 |
| &LITTLE_CPU_SLEEP_1 |
| &CLUSTER_SLEEP_0>; |
| capacity-dmips-mhz = <607>; |
| dynamic-power-coefficient = <100>; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, |
| <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_0>; |
| L2_0: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| L3_0: l3-cache { |
| compatible = "cache"; |
| }; |
| }; |
| }; |
| |
| CPU1: cpu@100 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo385"; |
| reg = <0x0 0x100>; |
| enable-method = "psci"; |
| cpu-idle-states = <&LITTLE_CPU_SLEEP_0 |
| &LITTLE_CPU_SLEEP_1 |
| &CLUSTER_SLEEP_0>; |
| capacity-dmips-mhz = <607>; |
| dynamic-power-coefficient = <100>; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, |
| <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_100>; |
| L2_100: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU2: cpu@200 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo385"; |
| reg = <0x0 0x200>; |
| enable-method = "psci"; |
| cpu-idle-states = <&LITTLE_CPU_SLEEP_0 |
| &LITTLE_CPU_SLEEP_1 |
| &CLUSTER_SLEEP_0>; |
| capacity-dmips-mhz = <607>; |
| dynamic-power-coefficient = <100>; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, |
| <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_200>; |
| L2_200: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU3: cpu@300 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo385"; |
| reg = <0x0 0x300>; |
| enable-method = "psci"; |
| cpu-idle-states = <&LITTLE_CPU_SLEEP_0 |
| &LITTLE_CPU_SLEEP_1 |
| &CLUSTER_SLEEP_0>; |
| capacity-dmips-mhz = <607>; |
| dynamic-power-coefficient = <100>; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, |
| <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_300>; |
| L2_300: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU4: cpu@400 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo385"; |
| reg = <0x0 0x400>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| cpu-idle-states = <&BIG_CPU_SLEEP_0 |
| &BIG_CPU_SLEEP_1 |
| &CLUSTER_SLEEP_0>; |
| dynamic-power-coefficient = <396>; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| operating-points-v2 = <&cpu4_opp_table>; |
| interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, |
| <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_400>; |
| L2_400: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU5: cpu@500 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo385"; |
| reg = <0x0 0x500>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| cpu-idle-states = <&BIG_CPU_SLEEP_0 |
| &BIG_CPU_SLEEP_1 |
| &CLUSTER_SLEEP_0>; |
| dynamic-power-coefficient = <396>; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| operating-points-v2 = <&cpu4_opp_table>; |
| interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, |
| <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_500>; |
| L2_500: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU6: cpu@600 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo385"; |
| reg = <0x0 0x600>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| cpu-idle-states = <&BIG_CPU_SLEEP_0 |
| &BIG_CPU_SLEEP_1 |
| &CLUSTER_SLEEP_0>; |
| dynamic-power-coefficient = <396>; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| operating-points-v2 = <&cpu4_opp_table>; |
| interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, |
| <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_600>; |
| L2_600: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU7: cpu@700 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo385"; |
| reg = <0x0 0x700>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| cpu-idle-states = <&BIG_CPU_SLEEP_0 |
| &BIG_CPU_SLEEP_1 |
| &CLUSTER_SLEEP_0>; |
| dynamic-power-coefficient = <396>; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| operating-points-v2 = <&cpu4_opp_table>; |
| interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>, |
| <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_700>; |
| L2_700: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&CPU0>; |
| }; |
| |
| core1 { |
| cpu = <&CPU1>; |
| }; |
| |
| core2 { |
| cpu = <&CPU2>; |
| }; |
| |
| core3 { |
| cpu = <&CPU3>; |
| }; |
| |
| core4 { |
| cpu = <&CPU4>; |
| }; |
| |
| core5 { |
| cpu = <&CPU5>; |
| }; |
| |
| core6 { |
| cpu = <&CPU6>; |
| }; |
| |
| core7 { |
| cpu = <&CPU7>; |
| }; |
| }; |
| }; |
| |
| idle-states { |
| entry-method = "psci"; |
| |
| LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "little-power-down"; |
| arm,psci-suspend-param = <0x40000003>; |
| entry-latency-us = <350>; |
| exit-latency-us = <461>; |
| min-residency-us = <1890>; |
| local-timer-stop; |
| }; |
| |
| LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "little-rail-power-down"; |
| arm,psci-suspend-param = <0x40000004>; |
| entry-latency-us = <360>; |
| exit-latency-us = <531>; |
| min-residency-us = <3934>; |
| local-timer-stop; |
| }; |
| |
| BIG_CPU_SLEEP_0: cpu-sleep-1-0 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "big-power-down"; |
| arm,psci-suspend-param = <0x40000003>; |
| entry-latency-us = <264>; |
| exit-latency-us = <621>; |
| min-residency-us = <952>; |
| local-timer-stop; |
| }; |
| |
| BIG_CPU_SLEEP_1: cpu-sleep-1-1 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "big-rail-power-down"; |
| arm,psci-suspend-param = <0x40000004>; |
| entry-latency-us = <702>; |
| exit-latency-us = <1061>; |
| min-residency-us = <4488>; |
| local-timer-stop; |
| }; |
| |
| CLUSTER_SLEEP_0: cluster-sleep-0 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "cluster-power-down"; |
| arm,psci-suspend-param = <0x400000F4>; |
| entry-latency-us = <3263>; |
| exit-latency-us = <6562>; |
| min-residency-us = <9987>; |
| local-timer-stop; |
| }; |
| }; |
| }; |
| |
| cpu0_opp_table: cpu0_opp_table { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| cpu0_opp1: opp-300000000 { |
| opp-hz = /bits/ 64 <300000000>; |
| opp-peak-kBps = <800000 4800000>; |
| }; |
| |
| cpu0_opp2: opp-403200000 { |
| opp-hz = /bits/ 64 <403200000>; |
| opp-peak-kBps = <800000 4800000>; |
| }; |
| |
| cpu0_opp3: opp-480000000 { |
| opp-hz = /bits/ 64 <480000000>; |
| opp-peak-kBps = <800000 6451200>; |
| }; |
| |
| cpu0_opp4: opp-576000000 { |
| opp-hz = /bits/ 64 <576000000>; |
| opp-peak-kBps = <800000 6451200>; |
| }; |
| |
| cpu0_opp5: opp-652800000 { |
| opp-hz = /bits/ 64 <652800000>; |
| opp-peak-kBps = <800000 7680000>; |
| }; |
| |
| cpu0_opp6: opp-748800000 { |
| opp-hz = /bits/ 64 <748800000>; |
| opp-peak-kBps = <1804000 9216000>; |
| }; |
| |
| cpu0_opp7: opp-825600000 { |
| opp-hz = /bits/ 64 <825600000>; |
| opp-peak-kBps = <1804000 9216000>; |
| }; |
| |
| cpu0_opp8: opp-902400000 { |
| opp-hz = /bits/ 64 <902400000>; |
| opp-peak-kBps = <1804000 10444800>; |
| }; |
| |
| cpu0_opp9: opp-979200000 { |
| opp-hz = /bits/ 64 <979200000>; |
| opp-peak-kBps = <1804000 11980800>; |
| }; |
| |
| cpu0_opp10: opp-1056000000 { |
| opp-hz = /bits/ 64 <1056000000>; |
| opp-peak-kBps = <1804000 11980800>; |
| }; |
| |
| cpu0_opp11: opp-1132800000 { |
| opp-hz = /bits/ 64 <1132800000>; |
| opp-peak-kBps = <2188000 13516800>; |
| }; |
| |
| cpu0_opp12: opp-1228800000 { |
| opp-hz = /bits/ 64 <1228800000>; |
| opp-peak-kBps = <2188000 15052800>; |
| }; |
| |
| cpu0_opp13: opp-1324800000 { |
| opp-hz = /bits/ 64 <1324800000>; |
| opp-peak-kBps = <2188000 16588800>; |
| }; |
| |
| cpu0_opp14: opp-1420800000 { |
| opp-hz = /bits/ 64 <1420800000>; |
| opp-peak-kBps = <3072000 18124800>; |
| }; |
| |
| cpu0_opp15: opp-1516800000 { |
| opp-hz = /bits/ 64 <1516800000>; |
| opp-peak-kBps = <3072000 19353600>; |
| }; |
| |
| cpu0_opp16: opp-1612800000 { |
| opp-hz = /bits/ 64 <1612800000>; |
| opp-peak-kBps = <4068000 19353600>; |
| }; |
| |
| cpu0_opp17: opp-1689600000 { |
| opp-hz = /bits/ 64 <1689600000>; |
| opp-peak-kBps = <4068000 20889600>; |
| }; |
| |
| cpu0_opp18: opp-1766400000 { |
| opp-hz = /bits/ 64 <1766400000>; |
| opp-peak-kBps = <4068000 22425600>; |
| }; |
| }; |
| |
| cpu4_opp_table: cpu4_opp_table { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| cpu4_opp1: opp-300000000 { |
| opp-hz = /bits/ 64 <300000000>; |
| opp-peak-kBps = <800000 4800000>; |
| }; |
| |
| cpu4_opp2: opp-403200000 { |
| opp-hz = /bits/ 64 <403200000>; |
| opp-peak-kBps = <800000 4800000>; |
| }; |
| |
| cpu4_opp3: opp-480000000 { |
| opp-hz = /bits/ 64 <480000000>; |
| opp-peak-kBps = <1804000 4800000>; |
| }; |
| |
| cpu4_opp4: opp-576000000 { |
| opp-hz = /bits/ 64 <576000000>; |
| opp-peak-kBps = <1804000 4800000>; |
| }; |
| |
| cpu4_opp5: opp-652800000 { |
| opp-hz = /bits/ 64 <652800000>; |
| opp-peak-kBps = <1804000 4800000>; |
| }; |
| |
| cpu4_opp6: opp-748800000 { |
| opp-hz = /bits/ 64 <748800000>; |
| opp-peak-kBps = <1804000 4800000>; |
| }; |
| |
| cpu4_opp7: opp-825600000 { |
| opp-hz = /bits/ 64 <825600000>; |
| opp-peak-kBps = <2188000 9216000>; |
| }; |
| |
| cpu4_opp8: opp-902400000 { |
| opp-hz = /bits/ 64 <902400000>; |
| opp-peak-kBps = <2188000 9216000>; |
| }; |
| |
| cpu4_opp9: opp-979200000 { |
| opp-hz = /bits/ 64 <979200000>; |
| opp-peak-kBps = <2188000 9216000>; |
| }; |
| |
| cpu4_opp10: opp-1056000000 { |
| opp-hz = /bits/ 64 <1056000000>; |
| opp-peak-kBps = <3072000 9216000>; |
| }; |
| |
| cpu4_opp11: opp-1132800000 { |
| opp-hz = /bits/ 64 <1132800000>; |
| opp-peak-kBps = <3072000 11980800>; |
| }; |
| |
| cpu4_opp12: opp-1209600000 { |
| opp-hz = /bits/ 64 <1209600000>; |
| opp-peak-kBps = <4068000 11980800>; |
| }; |
| |
| cpu4_opp13: opp-1286400000 { |
| opp-hz = /bits/ 64 <1286400000>; |
| opp-peak-kBps = <4068000 11980800>; |
| }; |
| |
| cpu4_opp14: opp-1363200000 { |
| opp-hz = /bits/ 64 <1363200000>; |
| opp-peak-kBps = <4068000 15052800>; |
| }; |
| |
| cpu4_opp15: opp-1459200000 { |
| opp-hz = /bits/ 64 <1459200000>; |
| opp-peak-kBps = <4068000 15052800>; |
| }; |
| |
| cpu4_opp16: opp-1536000000 { |
| opp-hz = /bits/ 64 <1536000000>; |
| opp-peak-kBps = <5412000 15052800>; |
| }; |
| |
| cpu4_opp17: opp-1612800000 { |
| opp-hz = /bits/ 64 <1612800000>; |
| opp-peak-kBps = <5412000 15052800>; |
| }; |
| |
| cpu4_opp18: opp-1689600000 { |
| opp-hz = /bits/ 64 <1689600000>; |
| opp-peak-kBps = <5412000 19353600>; |
| }; |
| |
| cpu4_opp19: opp-1766400000 { |
| opp-hz = /bits/ 64 <1766400000>; |
| opp-peak-kBps = <6220000 19353600>; |
| }; |
| |
| cpu4_opp20: opp-1843200000 { |
| opp-hz = /bits/ 64 <1843200000>; |
| opp-peak-kBps = <6220000 19353600>; |
| }; |
| |
| cpu4_opp21: opp-1920000000 { |
| opp-hz = /bits/ 64 <1920000000>; |
| opp-peak-kBps = <7216000 19353600>; |
| }; |
| |
| cpu4_opp22: opp-1996800000 { |
| opp-hz = /bits/ 64 <1996800000>; |
| opp-peak-kBps = <7216000 20889600>; |
| }; |
| |
| cpu4_opp23: opp-2092800000 { |
| opp-hz = /bits/ 64 <2092800000>; |
| opp-peak-kBps = <7216000 20889600>; |
| }; |
| |
| cpu4_opp24: opp-2169600000 { |
| opp-hz = /bits/ 64 <2169600000>; |
| opp-peak-kBps = <7216000 20889600>; |
| }; |
| |
| cpu4_opp25: opp-2246400000 { |
| opp-hz = /bits/ 64 <2246400000>; |
| opp-peak-kBps = <7216000 20889600>; |
| }; |
| |
| cpu4_opp26: opp-2323200000 { |
| opp-hz = /bits/ 64 <2323200000>; |
| opp-peak-kBps = <7216000 20889600>; |
| }; |
| |
| cpu4_opp27: opp-2400000000 { |
| opp-hz = /bits/ 64 <2400000000>; |
| opp-peak-kBps = <7216000 22425600>; |
| }; |
| |
| cpu4_opp28: opp-2476800000 { |
| opp-hz = /bits/ 64 <2476800000>; |
| opp-peak-kBps = <7216000 22425600>; |
| }; |
| |
| cpu4_opp29: opp-2553600000 { |
| opp-hz = /bits/ 64 <2553600000>; |
| opp-peak-kBps = <7216000 22425600>; |
| }; |
| |
| cpu4_opp30: opp-2649600000 { |
| opp-hz = /bits/ 64 <2649600000>; |
| opp-peak-kBps = <7216000 22425600>; |
| }; |
| |
| cpu4_opp31: opp-2745600000 { |
| opp-hz = /bits/ 64 <2745600000>; |
| opp-peak-kBps = <7216000 25497600>; |
| }; |
| |
| cpu4_opp32: opp-2803200000 { |
| opp-hz = /bits/ 64 <2803200000>; |
| opp-peak-kBps = <7216000 25497600>; |
| }; |
| }; |
| |
| pmu { |
| compatible = "arm,armv8-pmuv3"; |
| interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| |
| clocks { |
| xo_board: xo-board { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <38400000>; |
| clock-output-names = "xo_board"; |
| }; |
| |
| sleep_clk: sleep-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32764>; |
| }; |
| }; |
| |
| firmware { |
| scm { |
| compatible = "qcom,scm-sdm845", "qcom,scm"; |
| }; |
| }; |
| |
| adsp_pas: remoteproc-adsp { |
| compatible = "qcom,sdm845-adsp-pas"; |
| |
| interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, |
| <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
| <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, |
| <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, |
| <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "wdog", "fatal", "ready", |
| "handover", "stop-ack"; |
| |
| clocks = <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "xo"; |
| |
| memory-region = <&adsp_mem>; |
| |
| qcom,smem-states = <&adsp_smp2p_out 0>; |
| qcom,smem-state-names = "stop"; |
| |
| status = "disabled"; |
| |
| glink-edge { |
| interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; |
| label = "lpass"; |
| qcom,remote-pid = <2>; |
| mboxes = <&apss_shared 8>; |
| |
| apr { |
| compatible = "qcom,apr-v2"; |
| qcom,glink-channels = "apr_audio_svc"; |
| qcom,apr-domain = <APR_DOMAIN_ADSP>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| qcom,intents = <512 20>; |
| |
| apr-service@3 { |
| reg = <APR_SVC_ADSP_CORE>; |
| compatible = "qcom,q6core"; |
| qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; |
| }; |
| |
| q6afe: apr-service@4 { |
| compatible = "qcom,q6afe"; |
| reg = <APR_SVC_AFE>; |
| qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; |
| q6afedai: dais { |
| compatible = "qcom,q6afe-dais"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #sound-dai-cells = <1>; |
| }; |
| }; |
| |
| q6asm: apr-service@7 { |
| compatible = "qcom,q6asm"; |
| reg = <APR_SVC_ASM>; |
| qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; |
| q6asmdai: dais { |
| compatible = "qcom,q6asm-dais"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #sound-dai-cells = <1>; |
| iommus = <&apps_smmu 0x1821 0x0>; |
| }; |
| }; |
| |
| q6adm: apr-service@8 { |
| compatible = "qcom,q6adm"; |
| reg = <APR_SVC_ADM>; |
| qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; |
| q6routing: routing { |
| compatible = "qcom,q6adm-routing"; |
| #sound-dai-cells = <0>; |
| }; |
| }; |
| }; |
| |
| fastrpc { |
| compatible = "qcom,fastrpc"; |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| label = "adsp"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| compute-cb@3 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <3>; |
| iommus = <&apps_smmu 0x1823 0x0>; |
| }; |
| |
| compute-cb@4 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <4>; |
| iommus = <&apps_smmu 0x1824 0x0>; |
| }; |
| }; |
| }; |
| }; |
| |
| cdsp_pas: remoteproc-cdsp { |
| compatible = "qcom,sdm845-cdsp-pas"; |
| |
| interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, |
| <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
| <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, |
| <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, |
| <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "wdog", "fatal", "ready", |
| "handover", "stop-ack"; |
| |
| clocks = <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "xo"; |
| |
| memory-region = <&cdsp_mem>; |
| |
| qcom,smem-states = <&cdsp_smp2p_out 0>; |
| qcom,smem-state-names = "stop"; |
| |
| status = "disabled"; |
| |
| glink-edge { |
| interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; |
| label = "turing"; |
| qcom,remote-pid = <5>; |
| mboxes = <&apss_shared 4>; |
| fastrpc { |
| compatible = "qcom,fastrpc"; |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| label = "cdsp"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| compute-cb@1 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <1>; |
| iommus = <&apps_smmu 0x1401 0x30>; |
| }; |
| |
| compute-cb@2 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <2>; |
| iommus = <&apps_smmu 0x1402 0x30>; |
| }; |
| |
| compute-cb@3 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <3>; |
| iommus = <&apps_smmu 0x1403 0x30>; |
| }; |
| |
| compute-cb@4 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <4>; |
| iommus = <&apps_smmu 0x1404 0x30>; |
| }; |
| |
| compute-cb@5 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <5>; |
| iommus = <&apps_smmu 0x1405 0x30>; |
| }; |
| |
| compute-cb@6 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <6>; |
| iommus = <&apps_smmu 0x1406 0x30>; |
| }; |
| |
| compute-cb@7 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <7>; |
| iommus = <&apps_smmu 0x1407 0x30>; |
| }; |
| |
| compute-cb@8 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <8>; |
| iommus = <&apps_smmu 0x1408 0x30>; |
| }; |
| }; |
| }; |
| }; |
| |
| tcsr_mutex: hwlock { |
| compatible = "qcom,tcsr-mutex"; |
| syscon = <&tcsr_mutex_regs 0 0x1000>; |
| #hwlock-cells = <1>; |
| }; |
| |
| smem { |
| compatible = "qcom,smem"; |
| memory-region = <&smem_mem>; |
| hwlocks = <&tcsr_mutex 3>; |
| }; |
| |
| smp2p-cdsp { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <94>, <432>; |
| |
| interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; |
| |
| mboxes = <&apss_shared 6>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <5>; |
| |
| cdsp_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| cdsp_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| smp2p-lpass { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <443>, <429>; |
| |
| interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; |
| |
| mboxes = <&apss_shared 10>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <2>; |
| |
| adsp_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| adsp_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| smp2p-mpss { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <435>, <428>; |
| interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&apss_shared 14>; |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <1>; |
| |
| modem_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| modem_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| ipa_smp2p_out: ipa-ap-to-modem { |
| qcom,entry-name = "ipa"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| ipa_smp2p_in: ipa-modem-to-ap { |
| qcom,entry-name = "ipa"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| smp2p-slpi { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <481>, <430>; |
| interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&apss_shared 26>; |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <3>; |
| |
| slpi_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| slpi_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| soc: soc@0 { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0 0 0 0 0x10 0>; |
| dma-ranges = <0 0 0 0 0x10 0>; |
| compatible = "simple-bus"; |
| |
| gcc: clock-controller@100000 { |
| compatible = "qcom,gcc-sdm845"; |
| reg = <0 0x00100000 0 0x1f0000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| }; |
| |
| qfprom@784000 { |
| compatible = "qcom,qfprom"; |
| reg = <0 0x00784000 0 0x8ff>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| qusb2p_hstx_trim: hstx-trim-primary@1eb { |
| reg = <0x1eb 0x1>; |
| bits = <1 4>; |
| }; |
| |
| qusb2s_hstx_trim: hstx-trim-secondary@1eb { |
| reg = <0x1eb 0x2>; |
| bits = <6 4>; |
| }; |
| }; |
| |
| rng: rng@793000 { |
| compatible = "qcom,prng-ee"; |
| reg = <0 0x00793000 0 0x1000>; |
| clocks = <&gcc GCC_PRNG_AHB_CLK>; |
| clock-names = "core"; |
| }; |
| |
| qup_opp_table: qup-opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-19200000 { |
| opp-hz = /bits/ 64 <19200000>; |
| required-opps = <&rpmhpd_opp_min_svs>; |
| }; |
| |
| opp-75000000 { |
| opp-hz = /bits/ 64 <75000000>; |
| required-opps = <&rpmhpd_opp_low_svs>; |
| }; |
| |
| opp-100000000 { |
| opp-hz = /bits/ 64 <100000000>; |
| required-opps = <&rpmhpd_opp_svs>; |
| }; |
| }; |
| |
| qupv3_id_0: geniqup@8c0000 { |
| compatible = "qcom,geni-se-qup"; |
| reg = <0 0x008c0000 0 0x6000>; |
| clock-names = "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| status = "disabled"; |
| |
| i2c0: i2c@880000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00880000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c0_default>; |
| interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| spi0: spi@880000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00880000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi0_default>; |
| interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart0: serial@880000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00880000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart0_default>; |
| interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@884000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00884000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c1_default>; |
| interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@884000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00884000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi1_default>; |
| interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@884000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00884000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart1_default>; |
| interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@888000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00888000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c2_default>; |
| interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@888000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00888000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi2_default>; |
| interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@888000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00888000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart2_default>; |
| interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@88c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x0088c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c3_default>; |
| interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| spi3: spi@88c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x0088c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi3_default>; |
| interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@88c000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x0088c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart3_default>; |
| interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@890000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00890000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c4_default>; |
| interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| spi4: spi@890000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00890000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi4_default>; |
| interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@890000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00890000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart4_default>; |
| interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c@894000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00894000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c5_default>; |
| interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| spi5: spi@894000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00894000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi5_default>; |
| interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart5: serial@894000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00894000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart5_default>; |
| interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| i2c6: i2c@898000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00898000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c6_default>; |
| interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| spi6: spi@898000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00898000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi6_default>; |
| interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart6: serial@898000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00898000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart6_default>; |
| interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| i2c7: i2c@89c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x0089c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c7_default>; |
| interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| spi7: spi@89c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x0089c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi7_default>; |
| interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart7: serial@89c000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x0089c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart7_default>; |
| interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| }; |
| |
| qupv3_id_1: geniqup@ac0000 { |
| compatible = "qcom,geni-se-qup"; |
| reg = <0 0x00ac0000 0 0x6000>; |
| clock-names = "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| status = "disabled"; |
| |
| i2c8: i2c@a80000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a80000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c8_default>; |
| interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| spi8: spi@a80000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a80000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi8_default>; |
| interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart8: serial@a80000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00a80000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart8_default>; |
| interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| i2c9: i2c@a84000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a84000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c9_default>; |
| interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| spi9: spi@a84000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a84000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi9_default>; |
| interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart9: serial@a84000 { |
| compatible = "qcom,geni-debug-uart"; |
| reg = <0 0x00a84000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart9_default>; |
| interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| i2c10: i2c@a88000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a88000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c10_default>; |
| interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| spi10: spi@a88000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a88000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi10_default>; |
| interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart10: serial@a88000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00a88000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart10_default>; |
| interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| i2c11: i2c@a8c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a8c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c11_default>; |
| interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| spi11: spi@a8c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a8c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi11_default>; |
| interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart11: serial@a8c000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00a8c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart11_default>; |
| interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| i2c12: i2c@a90000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a90000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c12_default>; |
| interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| spi12: spi@a90000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a90000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi12_default>; |
| interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart12: serial@a90000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00a90000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart12_default>; |
| interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| i2c13: i2c@a94000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a94000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c13_default>; |
| interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| spi13: spi@a94000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a94000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi13_default>; |
| interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart13: serial@a94000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00a94000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart13_default>; |
| interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| i2c14: i2c@a98000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a98000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c14_default>; |
| interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| spi14: spi@a98000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a98000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi14_default>; |
| interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart14: serial@a98000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00a98000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart14_default>; |
| interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| i2c15: i2c@a9c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a9c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c15_default>; |
| interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| |
| spi15: spi@a9c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a9c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi15_default>; |
| interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart15: serial@a9c000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00a9c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart15_default>; |
| interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SDM845_CX>; |
| operating-points-v2 = <&qup_opp_table>; |
| status = "disabled"; |
| }; |
| }; |
| |
| system-cache-controller@1100000 { |
| compatible = "qcom,sdm845-llcc"; |
| reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; |
| reg-names = "llcc_base", "llcc_broadcast_base"; |
| interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pcie0: pci@1c00000 { |
| compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; |
| reg = <0 0x01c00000 0 0x2000>, |
| <0 0x60000000 0 0xf1d>, |
| <0 0x60000f20 0 0xa8>, |
| <0 0x60100000 0 0x100000>; |
| reg-names = "parf", "dbi", "elbi", "config"; |
| device_type = "pci"; |
| linux,pci-domain = <0>; |
| bus-range = <0x00 0xff>; |
| num-lanes = <1>; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, |
| <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>; |
| |
| interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "msi"; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0x7>; |
| interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ |
| <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ |
| <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ |
| <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ |
| |
| clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, |
| <&gcc GCC_PCIE_0_AUX_CLK>, |
| <&gcc GCC_PCIE_0_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, |
| <&gcc GCC_PCIE_0_SLV_AXI_CLK>, |
| <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, |
| <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; |
| clock-names = "pipe", |
| "aux", |
| "cfg", |
| "bus_master", |
| "bus_slave", |
| "slave_q2a", |
| "tbu"; |
| |
| iommus = <&apps_smmu 0x1c10 0xf>; |
| iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, |
| <0x100 &apps_smmu 0x1c11 0x1>, |
| <0x200 &apps_smmu 0x1c12 0x1>, |
| <0x300 &apps_smmu 0x1c13 0x1>, |
| <0x400 &apps_smmu 0x1c14 0x1>, |
| <0x500 &apps_smmu 0x1c15 0x1>, |
| <0x600 &apps_smmu 0x1c16 0x1>, |
| <0x700 &apps_smmu 0x1c17 0x1>, |
| <0x800 &apps_smmu 0x1c18 0x1>, |
| <0x900 &apps_smmu 0x1c19 0x1>, |
| <0xa00 &apps_smmu 0x1c1a 0x1>, |
| <0xb00 &apps_smmu 0x1c1b 0x1>, |
| <0xc00 &apps_smmu 0x1c1c 0x1>, |
| <0xd00 &apps_smmu 0x1c1d 0x1>, |
| <0xe00 &apps_smmu 0x1c1e 0x1>, |
| <0xf00 &apps_smmu 0x1c1f 0x1>; |
| |
| resets = <&gcc GCC_PCIE_0_BCR>; |
| reset-names = "pci"; |
| |
| power-domains = <&gcc PCIE_0_GDSC>; |
| |
| phys = <&pcie0_lane>; |
| phy-names = "pciephy"; |
| |
| status = "disabled"; |
| }; |
| |
| pcie0_phy: phy@1c06000 { |
| compatible = "qcom,sdm845-qmp-pcie-phy"; |
| reg = <0 0x01c06000 0 0x18c>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, |
| <&gcc GCC_PCIE_0_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_0_CLKREF_CLK>, |
| <&gcc GCC_PCIE_PHY_REFGEN_CLK>; |
| clock-names = "aux", "cfg_ahb", "ref", "refgen"; |
| |
| resets = <&gcc GCC_PCIE_0_PHY_BCR>; |
| reset-names = "phy"; |
| |
| assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; |
| assigned-clock-rates = <100000000>; |
| |
| status = "disabled"; |
| |
| pcie0_lane: lanes@1c06200 { |
| reg = <0 0x01c06200 0 0x128>, |
| <0 0x01c06400 0 0x1fc>, |
| <0 0x01c06800 0 0x218>, |
| <0 0x01c06600 0 0x70>; |
| clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; |
| clock-names = "pipe0"; |
| |
| #phy-cells = <0>; |
| clock-output-names = "pcie_0_pipe_clk"; |
| }; |
| }; |
| |
| pcie1: pci@1c08000 { |
| compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; |
| reg = <0 0x01c08000 0 0x2000>, |
| <0 0x40000000 0 0xf1d>, |
| <0 0x40000f20 0 0xa8>, |
| <0 0x40100000 0 0x100000>; |
| reg-names = "parf", "dbi", "elbi", "config"; |
| device_type = "pci"; |
| linux,pci-domain = <1>; |
| bus-range = <0x00 0xff>; |
| num-lanes = <1>; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, |
| <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; |
| |
| interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "msi"; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0x7>; |
| interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ |
| <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ |
| <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ |
| <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ |
| |
| clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, |
| <&gcc GCC_PCIE_1_AUX_CLK>, |
| <&gcc GCC_PCIE_1_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, |
| <&gcc GCC_PCIE_1_SLV_AXI_CLK>, |
| <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, |
| <&gcc GCC_PCIE_1_CLKREF_CLK>, |
| <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; |
| clock-names = "pipe", |
| "aux", |
| "cfg", |
| "bus_master", |
| "bus_slave", |
| "slave_q2a", |
| "ref", |
| "tbu"; |
| |
| assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; |
| assigned-clock-rates = <19200000>; |
| |
| iommus = <&apps_smmu 0x1c00 0xf>; |
| iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, |
| <0x100 &apps_smmu 0x1c01 0x1>, |
| <0x200 &apps_smmu 0x1c02 0x1>, |
| <0x300 &apps_smmu 0x1c03 0x1>, |
| <0x400 &apps_smmu 0x1c04 0x1>, |
| <0x500 &apps_smmu 0x1c05 0x1>, |
| <0x600 &apps_smmu 0x1c06 0x1>, |
| <0x700 &apps_smmu 0x1c07 0x1>, |
| <0x800 &apps_smmu 0x1c08 0x1>, |
| <0x900 &apps_smmu 0x1c09 0x1>, |
| <0xa00 &apps_smmu 0x1c0a 0x1>, |
| <0xb00 &apps_smmu 0x1c0b 0x1>, |
| <0xc00 &apps_smmu 0x1c0c 0x1>, |
| <0xd00 &apps_smmu 0x1c0d 0x1>, |
| <0xe00 &apps_smmu 0x1c0e 0x1>, |
| <0xf00 &apps_smmu 0x1c0f 0x1>; |
| |
| resets = <&gcc GCC_PCIE_1_BCR>; |
| reset-names = "pci"; |
| |
| power-domains = <&gcc PCIE_1_GDSC>; |
| |
| phys = <&pcie1_lane>; |
| phy-names = "pciephy"; |
| |
| status = "disabled"; |
| }; |
| |
| pcie1_phy: phy@1c0a000 { |
| compatible = "qcom,sdm845-qhp-pcie-phy"; |
| reg = <0 0x01c0a000 0 0x800>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, |
| <&gcc GCC_PCIE_1_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_1_CLKREF_CLK>, |
| <&gcc GCC_PCIE_PHY_REFGEN_CLK>; |
| clock-names = "aux", "cfg_ahb", "ref", "refgen"; |
| |
| resets = <&gcc GCC_PCIE_1_PHY_BCR>; |
| reset-names = "phy"; |
| |
| assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; |
| assigned-clock-rates = <100000000>; |
| |
| status = "disabled"; |
| |
| pcie1_lane: lanes@1c06200 { |
| reg = <0 0x01c0a800 0 0x800>, |
| <0 0x01c0a800 0 0x800>, |
| <0 0x01c0b800 0 0x400>; |
| clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; |
| clock-names = "pipe0"; |
| |
| #phy-cells = <0>; |
| clock-output-names = "pcie_1_pipe_clk"; |
| }; |
| }; |
| |
| mem_noc: interconnect@1380000 { |
| compatible = "qcom,sdm845-mem-noc"; |
| reg = <0 0x01380000 0 0x27200>; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| dc_noc: interconnect@14e0000 { |
| compatible = "qcom,sdm845-dc-noc"; |
| reg = <0 0x014e0000 0 0x400>; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| config_noc: interconnect@1500000 { |
| compatible = "qcom,sdm845-config-noc"; |
| reg = <0 0x01500000 0 0x5080>; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| system_noc: interconnect@1620000 { |
| compatible = "qcom,sdm845-system-noc"; |
| reg = <0 0x01620000 0 0x18080>; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| aggre1_noc: interconnect@16e0000 { |
| compatible = "qcom,sdm845-aggre1-noc"; |
| reg = <0 0x016e0000 0 0x15080>; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| aggre2_noc: interconnect@1700000 { |
| compatible = "qcom,sdm845-aggre2-noc"; |
| reg = <0 0x01700000 0 0x1f300>; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| mmss_noc: interconnect@1740000 { |
| compatible = "qcom,sdm845-mmss-noc"; |
| reg = <0 0x01740000 0 0x1c100>; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| ufs_mem_hc: ufshc@1d84000 { |
| compatible = "qcom,sdm845-ufshc", "qcom,ufshc", |
| "jedec,ufs-2.0"; |
| reg = <0 0x01d84000 0 0x2500>, |
| <0 0x01d90000 0 0x8000>; |
| reg-names = "std", "ice"; |
| interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; |
| phys = <&ufs_mem_phy_lanes>; |
| phy-names = "ufsphy"; |
| lanes-per-direction = <2>; |
| power-domains = <&gcc UFS_PHY_GDSC>; |
| #reset-cells = <1>; |
| resets = <&gcc GCC_UFS_PHY_BCR>; |
| reset-names = "rst"; |
| |
| iommus = <&apps_smmu 0x100 0xf>; |
| |
| clock-names = |
| "core_clk", |
| "bus_aggr_clk", |
| "iface_clk", |
| "core_clk_unipro", |
| "ref_clk", |
| "tx_lane0_sync_clk", |
| "rx_lane0_sync_clk", |
| "rx_lane1_sync_clk", |
| "ice_core_clk"; |
| clocks = |
| <&gcc GCC_UFS_PHY_AXI_CLK>, |
| <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, |
| <&gcc GCC_UFS_PHY_AHB_CLK>, |
| <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, |
| <&rpmhcc RPMH_CXO_CLK>, |
| <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, |
| <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, |
| <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, |
| <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; |
| freq-table-hz = |
| <50000000 200000000>, |
| <0 0>, |
| <0 0>, |
| <37500000 150000000>, |
| <0 0>, |
| <0 0>, |
| <0 0>, |
| <0 0>, |
| <0 300000000>; |
| |
| status = "disabled"; |
| }; |
| |
| ufs_mem_phy: phy@1d87000 { |
| compatible = "qcom,sdm845-qmp-ufs-phy"; |
| reg = <0 0x01d87000 0 0x18c>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| clock-names = "ref", |
| "ref_aux"; |
| clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, |
| <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; |
| |
| resets = <&ufs_mem_hc 0>; |
| reset-names = "ufsphy"; |
| status = "disabled"; |
| |
| ufs_mem_phy_lanes: lanes@1d87400 { |
| reg = <0 0x01d87400 0 0x108>, |
| <0 0x01d87600 0 0x1e0>, |
| <0 0x01d87c00 0 0x1dc>, |
| <0 0x01d87800 0 0x108>, |
| <0 0x01d87a00 0 0x1e0>; |
| #phy-cells = <0>; |
| }; |
| }; |
| |
| ipa: ipa@1e40000 { |
| compatible = "qcom,sdm845-ipa"; |
| |
| iommus = <&apps_smmu 0x720 0x3>; |
| reg = <0 0x1e40000 0 0x7000>, |
| <0 0x1e47000 0 0x2000>, |
| <0 0x1e04000 0 0x2c000>; |
| reg-names = "ipa-reg", |
| "ipa-shared", |
| "gsi"; |
| |
| interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>, |
| <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, |
| <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
| <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "ipa", |
| "gsi", |
| "ipa-clock-query", |
| "ipa-setup-ready"; |
| |
| clocks = <&rpmhcc RPMH_IPA_CLK>; |
| clock-names = "core"; |
| |
| interconnects = <&aggre2_noc MASTER_IPA &mem_noc SLAVE_EBI1>, |
| <&aggre2_noc MASTER_IPA &system_noc SLAVE_IMEM>, |
| <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; |
| interconnect-names = "memory", |
| "imem", |
| "config"; |
| |
| qcom,smem-states = <&ipa_smp2p_out 0>, |
| <&ipa_smp2p_out 1>; |
| qcom,smem-state-names = "ipa-clock-enabled-valid", |
| "ipa-clock-enabled"; |
| |
| modem-remoteproc = <&mss_pil>; |
| |
| status = "disabled"; |
| }; |
| |
| tcsr_mutex_regs: syscon@1f40000 { |
| compatible = "syscon"; |
| reg = <0 0x01f40000 0 0x40000>; |
| }; |
| |
| tlmm: pinctrl@3400000 { |
| compatible = "qcom,sdm845-pinctrl"; |
| reg = <0 0x03400000 0 0xc00000>; |
| interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&tlmm 0 0 150>; |
| wakeup-parent = <&pdc_intc>; |
| |
| cci0_default: cci0-default { |
| /* SDA, SCL */ |
| pins = "gpio17", "gpio18"; |
| function = "cci_i2c"; |
| |
| bias-pull-up; |
| drive-strength = <2>; /* 2 mA */ |
| }; |
| |
| cci0_sleep: cci0-sleep { |
| /* SDA, SCL */ |
| pins = "gpio17", "gpio18"; |
| function = "cci_i2c"; |
| |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; |
| }; |
| |
| cci1_default: cci1-default { |
| /* SDA, SCL */ |
| pins = "gpio19", "gpio20"; |
| function = "cci_i2c"; |
| |
| bias-pull-up; |
| drive-strength = <2>; /* 2 mA */ |
| }; |
| |
| cci1_sleep: cci1-sleep { |
| /* SDA, SCL */ |
| pins = "gpio19", "gpio20"; |
| function = "cci_i2c"; |
| |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; |
| }; |
| |
| qspi_clk: qspi-clk { |
| pinmux { |
| pins = "gpio95"; |
| function = "qspi_clk"; |
| }; |
| }; |
| |
| qspi_cs0: qspi-cs0 { |
| pinmux { |
| pins = "gpio90"; |
| function = "qspi_cs"; |
| }; |
| }; |
| |
| qspi_cs1: qspi-cs1 { |
| pinmux { |
| pins = "gpio89"; |
| function = "qspi_cs"; |
| }; |
| }; |
| |
| qspi_data01: qspi-data01 { |
| pinmux-data { |
| pins = "gpio91", "gpio92"; |
| function = "qspi_data"; |
| }; |
| }; |
| |
| qspi_data12: qspi-data12 { |
| pinmux-data { |
| pins = "gpio93", "gpio94"; |
| function = "qspi_data"; |
| }; |
| }; |
| |
| qup_i2c0_default: qup-i2c0-default { |
| pinmux { |
| pins = "gpio0", "gpio1"; |
| function = "qup0"; |
| }; |
| }; |
| |
| qup_i2c1_default: qup-i2c1-default { |
| pinmux { |
| pins = "gpio17", "gpio18"; |
| function = "qup1"; |
| }; |
| }; |
| |
| qup_i2c2_default: qup-i2c2-default { |
| pinmux { |
| pins = "gpio27", "gpio28"; |
| function = "qup2"; |
| }; |
| }; |
| |
| qup_i2c3_default: qup-i2c3-default { |
| pinmux { |
| pins = "gpio41", "gpio42"; |
| function = "qup3"; |
| }; |
| }; |
| |
| qup_i2c4_default: qup-i2c4-default { |
| pinmux { |
| pins = "gpio89", "gpio90"; |
| function = "qup4"; |
| }; |
| }; |
| |
| qup_i2c5_default: qup-i2c5-default { |
| pinmux { |
| pins = "gpio85", "gpio86"; |
| function = "qup5"; |
| }; |
| }; |
| |
| qup_i2c6_default: qup-i2c6-default { |
| pinmux { |
| pins = "gpio45", "gpio46"; |
| function = "qup6"; |
| }; |
| }; |
| |
| qup_i2c7_default: qup-i2c7-default { |
| pinmux { |
| pins = "gpio93", "gpio94"; |
| function = "qup7"; |
| }; |
| }; |
| |
| qup_i2c8_default: qup-i2c8-default { |
| pinmux { |
| pins = "gpio65", "gpio66"; |
| function = "qup8"; |
| }; |
| }; |
| |
| qup_i2c9_default: qup-i2c9-default { |
| pinmux { |
| pins = "gpio6", "gpio7"; |
| function = "qup9"; |
| }; |
| }; |
| |
| qup_i2c10_default: qup-i2c10-default { |
| pinmux { |
| pins = "gpio55", "gpio56"; |
| function = "qup10"; |
| }; |
| }; |
| |
| qup_i2c11_default: qup-i2c11-default { |
| pinmux { |
| pins = "gpio31", "gpio32"; |
| function = "qup11"; |
| }; |
| }; |
| |
| qup_i2c12_default: qup-i2c12-default { |
| pinmux { |
| pins = "gpio49", "gpio50"; |
| function = "qup12"; |
| }; |
| }; |
| |
| qup_i2c13_default: qup-i2c13-default { |
| pinmux { |
| pins = "gpio105", "gpio106"; |
| function = "qup13"; |
| }; |
| }; |
| |
| qup_i2c14_default: qup-i2c14-default { |
| pinmux { |
| pins = "gpio33", "gpio34"; |
| function = "qup14"; |
| }; |
| }; |
| |
| qup_i2c15_default: qup-i2c15-default { |
| pinmux { |
| pins = "gpio81", "gpio82"; |
| function = "qup15"; |
| }; |
| }; |
| |
| qup_spi0_default: qup-spi0-default { |
| pinmux { |
| pins = "gpio0", "gpio1", |
| "gpio2", "gpio3"; |
| function = "qup0"; |
| }; |
| }; |
| |
| qup_spi1_default: qup-spi1-default { |
| pinmux { |
| pins = "gpio17", "gpio18", |
| "gpio19", "gpio20"; |
| function = "qup1"; |
| }; |
| }; |
| |
| qup_spi2_default: qup-spi2-default { |
| pinmux { |
| pins = "gpio27", "gpio28", |
| "gpio29", "gpio30"; |
| function = "qup2"; |
| }; |
| }; |
| |
| qup_spi3_default: qup-spi3-default { |
| pinmux { |
| pins = "gpio41", "gpio42", |
| "gpio43", "gpio44"; |
| function = "qup3"; |
| }; |
| }; |
| |
| qup_spi4_default: qup-spi4-default { |
| pinmux { |
| pins = "gpio89", "gpio90", |
| "gpio91", "gpio92"; |
| function = "qup4"; |
| }; |
| }; |
| |
| qup_spi5_default: qup-spi5-default { |
| pinmux { |
| pins = "gpio85", "gpio86", |
| "gpio87", "gpio88"; |
| function = "qup5"; |
| }; |
| }; |
| |
| qup_spi6_default: qup-spi6-default { |
| pinmux { |
| pins = "gpio45", "gpio46", |
| "gpio47", "gpio48"; |
| function = "qup6"; |
| }; |
| }; |
| |
| qup_spi7_default: qup-spi7-default { |
| pinmux { |
| pins = "gpio93", "gpio94", |
| "gpio95", "gpio96"; |
| function = "qup7"; |
| }; |
| }; |
| |
| qup_spi8_default: qup-spi8-default { |
| pinmux { |
| pins = "gpio65", "gpio66", |
| "gpio67", "gpio68"; |
| function = "qup8"; |
| }; |
| }; |
| |
| qup_spi9_default: qup-spi9-default { |
| pinmux { |
| pins = "gpio6", "gpio7", |
| "gpio4", "gpio5"; |
| function = "qup9"; |
| }; |
| }; |
| |
| qup_spi10_default: qup-spi10-default { |
| pinmux { |
| pins = "gpio55", "gpio56", |
| "gpio53", "gpio54"; |
| function = "qup10"; |
| }; |
| }; |
| |
| qup_spi11_default: qup-spi11-default { |
| pinmux { |
| pins = "gpio31", "gpio32", |
| "gpio33", "gpio34"; |
| function = "qup11"; |
| }; |
| }; |
| |
| qup_spi12_default: qup-spi12-default { |
| pinmux { |
| pins = "gpio49", "gpio50", |
| "gpio51", "gpio52"; |
| function = "qup12"; |
| }; |
| }; |
| |
| qup_spi13_default: qup-spi13-default { |
| pinmux { |
| pins = "gpio105", "gpio106", |
| "gpio107", "gpio108"; |
| function = "qup13"; |
| }; |
| }; |
| |
| qup_spi14_default: qup-spi14-default { |
| pinmux { |
| pins = "gpio33", "gpio34", |
| "gpio31", "gpio32"; |
| function = "qup14"; |
| }; |
| }; |
| |
| qup_spi15_default: qup-spi15-default { |
| pinmux { |
| pins = "gpio81", "gpio82", |
| "gpio83", "gpio84"; |
| function = "qup15"; |
| }; |
| }; |
| |
| qup_uart0_default: qup-uart0-default { |
| pinmux { |
| pins = "gpio2", "gpio3"; |
| function = "qup0"; |
| }; |
| }; |
| |
| qup_uart1_default: qup-uart1-default { |
| pinmux { |
| pins = "gpio19", "gpio20"; |
| function = "qup1"; |
| }; |
| }; |
| |
| qup_uart2_default: qup-uart2-default { |
| pinmux { |
| pins = "gpio29", "gpio30"; |
| function = "qup2"; |
| }; |
| }; |
| |
| qup_uart3_default: qup-uart3-default { |
| pinmux { |
| pins = "gpio43", "gpio44"; |
| function = "qup3"; |
| }; |
| }; |
| |
| qup_uart4_default: qup-uart4-default { |
| pinmux { |
| pins = "gpio91", "gpio92"; |
| function = "qup4"; |
| }; |
| }; |
| |
| qup_uart5_default: qup-uart5-default { |
| pinmux { |
| pins = "gpio87", "gpio88"; |
| function = "qup5"; |
| }; |
| }; |
| |
| qup_uart6_default: qup-uart6-default { |
| pinmux { |
| pins = "gpio47", "gpio48"; |
| function = "qup6"; |
| }; |
| }; |
| |
| qup_uart7_default: qup-uart7-default { |
| pinmux { |
| pins = "gpio95", "gpio96"; |
| function = "qup7"; |
| }; |
| }; |
| |
| qup_uart8_default: qup-uart8-default { |
| pinmux { |
| pins = "gpio67", "gpio68"; |
| function = "qup8"; |
| }; |
| }; |
| |
| qup_uart9_default: qup-uart9-default { |
| pinmux { |
| pins = "gpio4", "gpio5"; |
| function = "qup9"; |
| }; |
| }; |
| |
| qup_uart10_default: qup-uart10-default { |
| pinmux { |
| pins = "gpio53", "gpio54"; |
| function = "qup10"; |
| }; |
| }; |
| |
| qup_uart11_default: qup-uart11-default { |
| pinmux { |
| pins = "gpio33", "gpio34"; |
| function = "qup11"; |
| }; |
| }; |
| |
| qup_uart12_default: qup-uart12-default { |
| pinmux { |
| pins = "gpio51", "gpio52"; |
| function = "qup12"; |
| }; |
| }; |
| |
| qup_uart13_default: qup-uart13-default { |
| pinmux { |
| pins = "gpio107", "gpio108"; |
| function = "qup13"; |
| }; |
| }; |
| |
| qup_uart14_default: qup-uart14-default { |
| pinmux { |
| pins = "gpio31", "gpio32"; |
| function = "qup14"; |
| }; |
| }; |
| |
| qup_uart15_default: qup-uart15-default { |
| pinmux { |
| pins = "gpio83", "gpio84"; |
| function = "qup15"; |
| }; |
| }; |
| |
| quat_mi2s_sleep: quat_mi2s_sleep { |
| mux { |
| pins = "gpio58", "gpio59"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio58", "gpio59"; |
| drive-strength = <2>; |
| bias-pull-down; |
| input-enable; |
| }; |
| }; |
| |
| quat_mi2s_active: quat_mi2s_active { |
| mux { |
| pins = "gpio58", "gpio59"; |
| function = "qua_mi2s"; |
| }; |
| |
| config { |
| pins = "gpio58", "gpio59"; |
| drive-strength = <8>; |
| bias-disable; |
| output-high; |
| }; |
| }; |
| |
| quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { |
| mux { |
| pins = "gpio60"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio60"; |
| drive-strength = <2>; |
| bias-pull-down; |
| input-enable; |
| }; |
| }; |
| |
| quat_mi2s_sd0_active: quat_mi2s_sd0_active { |
| mux { |
| pins = "gpio60"; |
| function = "qua_mi2s"; |
| }; |
| |
| config { |
| pins = "gpio60"; |
| drive-strength = <8>; |
| bias-disable; |
| }; |
| }; |
| |
| quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { |
| mux { |
| pins = "gpio61"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio61"; |
| drive-strength = <2>; |
| bias-pull-down; |
| input-enable; |
| }; |
| }; |
| |
| quat_mi2s_sd1_active: quat_mi2s_sd1_active { |
| mux { |
| pins = "gpio61"; |
| function = "qua_mi2s"; |
| }; |
| |
| config { |
| pins = "gpio61"; |
| drive-strength = <8>; |
| bias-disable; |
| }; |
| }; |
| |
| quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { |
| mux { |
| pins = "gpio62"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio62"; |
| drive-strength = <2>; |
| bias-pull-down; |
| input-enable; |
| }; |
| }; |
| |
| quat_mi2s_sd2_active: quat_mi2s_sd2_active { |
| mux { |
| pins = "gpio62"; |
| function = "qua_mi2s"; |
| }; |
| |
| config { |
| pins = "gpio62"; |
| drive-strength = <8>; |
| bias-disable; |
| }; |
| }; |
| |
| quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { |
| mux { |
| pins = "gpio63"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio63"; |
| drive-strength = <2>; |
| bias-pull-down; |
| input-enable; |
| }; |
| }; |
| |
| quat_mi2s_sd3_active: quat_mi2s_sd3_active { |
| mux { |
| pins = "gpio63"; |
| function = "qua_mi2s"; |
| }; |
| |
| config { |
| pins = "gpio63"; |
| drive-strength = <8>; |
| bias-disable; |
| }; |
| }; |
| }; |
| |
| mss_pil: remoteproc@4080000 { |
| compatible = "qcom,sdm845-mss-pil"; |
| reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; |
| reg-names = "qdsp6", "rmb"; |
| |
| interrupts-extended = |
| <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, |
| <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
| <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, |
| <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, |
| <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, |
| <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "wdog", "fatal", "ready", |
| "handover", "stop-ack", |
| "shutdown-ack"; |
| |
| clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, |
| <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, |
| <&gcc GCC_BOOT_ROM_AHB_CLK>, |
| <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, |
| <&gcc GCC_MSS_SNOC_AXI_CLK>, |
| <&gcc GCC_MSS_MFAB_AXIS_CLK>, |
| <&gcc GCC_PRNG_AHB_CLK>, |
| <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "iface", "bus", "mem", "gpll0_mss", |
| "snoc_axi", "mnoc_axi", "prng", "xo"; |
| |
| qcom,smem-states = <&modem_smp2p_out 0>; |
| qcom,smem-state-names = "stop"; |
| |
| resets = <&aoss_reset AOSS_CC_MSS_RESTART>, |
| <&pdc_reset PDC_MODEM_SYNC_RESET>; |
| reset-names = "mss_restart", "pdc_reset"; |
| |
| qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; |
| |
| power-domains = <&aoss_qmp 2>, |
| <&rpmhpd SDM845_CX>, |
| <&rpmhpd SDM845_MX>, |
| <&rpmhpd SDM845_MSS>; |
| power-domain-names = "load_state", "cx", "mx", "mss"; |
| |
| mba { |
| memory-region = <&mba_region>; |
| }; |
| |
| mpss { |
| memory-region = <&mpss_region>; |
| }; |
| |
| glink-edge { |
| interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; |
| label = "modem"; |
| qcom,remote-pid = <1>; |
| mboxes = <&apss_shared 12>; |
| }; |
| }; |
| |
| gpucc: clock-controller@5090000 { |
| compatible = "qcom,sdm845-gpucc"; |
| reg = <0 0x05090000 0 0x9000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&gcc GCC_GPU_GPLL0_CLK_SRC>, |
| <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; |
| clock-names = "bi_tcxo", |
| "gcc_gpu_gpll0_clk_src", |
| "gcc_gpu_gpll0_div_clk_src"; |
| }; |
| |
| stm@6002000 { |
| compatible = "arm,coresight-stm", "arm,primecell"; |
| reg = <0 0x06002000 0 0x1000>, |
| <0 0x16280000 0 0x180000>; |
| reg-names = "stm-base", "stm-stimulus-base"; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| stm_out: endpoint { |
| remote-endpoint = |
| <&funnel0_in7>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel@6041000 { |
| compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
| reg = <0 0x06041000 0 0x1000>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| funnel0_out: endpoint { |
| remote-endpoint = |
| <&merge_funnel_in0>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@7 { |
| reg = <7>; |
| funnel0_in7: endpoint { |
| remote-endpoint = <&stm_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel@6043000 { |
| compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
| reg = <0 0x06043000 0 0x1000>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| funnel2_out: endpoint { |
| remote-endpoint = |
| <&merge_funnel_in2>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@5 { |
| reg = <5>; |
| funnel2_in5: endpoint { |
| remote-endpoint = |
| <&apss_merge_funnel_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel@6045000 { |
| compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
| reg = <0 0x06045000 0 0x1000>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| merge_funnel_out: endpoint { |
| remote-endpoint = <&etf_in>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| merge_funnel_in0: endpoint { |
| remote-endpoint = |
| <&funnel0_out>; |
| }; |
| }; |
| |
| port@2 { |
| reg = <2>; |
| merge_funnel_in2: endpoint { |
| remote-endpoint = |
| <&funnel2_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| replicator@6046000 { |
| compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; |
| reg = <0 0x06046000 0 0x1000>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| replicator_out: endpoint { |
| remote-endpoint = <&etr_in>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| port { |
| replicator_in: endpoint { |
| remote-endpoint = <&etf_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| etf@6047000 { |
| compatible = "arm,coresight-tmc", "arm,primecell"; |
| reg = <0 0x06047000 0 0x1000>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| etf_out: endpoint { |
| remote-endpoint = |
| <&replicator_in>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@1 { |
| reg = <1>; |
| etf_in: endpoint { |
| remote-endpoint = |
| <&merge_funnel_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| etr@6048000 { |
| compatible = "arm,coresight-tmc", "arm,primecell"; |
| reg = <0 0x06048000 0 0x1000>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| arm,scatter-gather; |
| |
| in-ports { |
| port { |
| etr_in: endpoint { |
| remote-endpoint = |
| <&replicator_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@7040000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0 0x07040000 0 0x1000>; |
| |
| cpu = <&CPU0>; |
| |
| clocks = <&aoss_qmp>; |
| clo
|
