| commit | 0a19991f9c323942f4ce646f85e276b436d8acac | [log] [tgz] |
|---|---|---|
| author | Robert Richter <rrichter@cavium.com> | Wed Apr 12 10:31:15 2017 +0200 |
| committer | Robert Richter <rrichter@cavium.com> | Fri Aug 11 18:30:55 2017 +0200 |
| tree | cd36b8ecae911650394a9f80750e34ec562f8f19 | |
| parent | c8faa76d66f8e8b66b42b2edb05e4a3638acac14 [diff] |
iommu/arm-smmu, ACPI: Enable Cavium SMMU-v3 In next IORT spec release there will be a definition of a Cavium specific model. Until then, enable the Cavium SMMU using cpu id registers. Early silicon versions (A1) of Cavium's CN99xx SMMUv3 implementation must be enabled. For later silicon versions (B0) the iort change will be in place. Signed-off-by: Robert Richter <rrichter@cavium.com>