mfd: db8500-prcmu: Update stored DSI PLL divider value

Previously the DSI PLL divider rate was initialised statically and
assumed to be 1. Before the common clock framework was enabled for
ux500, a call to clk_set_rate() would always update the HW registers
no matter what the current setting was.

This patch makes sure the actual hw settings and the sw assumed
settings are matched.

Signed-off-by: Paer-Olof Haakansson <>
Signed-off-by: Ulf Hansson <>
signed-off-by: Lee Jones <>
Signed-off-by: Samuel Ortiz <>
1 file changed