| 02ae8ba96640 ("drm/i915/icl: Add Multi-segmented gamma support") |
| 795f672b88ba ("drm/i915: Expose full 1024 LUT entries on ivb+") |
| 514462caf757 ("drm/i915: Add 10bit LUT for ilk/snb") |
| c21ce2effc52 ("drm/i915: Implement split/10bit gamma for ivb/hsw") |
| 5bda1aca5d94 ("drm/i915: Don't use split gamma when we don't have to") |
| 320d41b33ade ("drm/i915: Extract ilk_lut_10()") |
| 502da13a72da ("drm/i915: Program EXT2 GC MAX registers") |
| 61eae851c92b ("drm/i915: Fix GCMAX color register programming") |
| c4128ce7d59e ("drm/i915: Skip the linear degamma LUT load on ICL+") |
| f65d5528c023 ("drm/i915: Extract ilk_color_check()") |
| 1eb631561120 ("drm/i915: Extract bdw_color_check()") |
| fbeb4f362213 ("drm/i915: Extract glk_color_check()") |
| 1b386cf84931 ("drm/i915: Extract icl_color_check()") |
| 3cdd5174cfc6 ("drm/i915: Extract chv_color_check()") |
| e98f35624ca4 ("drm/i915: Extract i9xx_color_check()") |
| 9d9cb9c18c70 ("drm/i915: Turn intel_color_check() into a vfunc") |
| e0510da05192 ("drm/i915: Extract check_luts()") |
| 5a0404408d32 ("drm/i915: Fix legacy gamma mode for ICL") |
| f19d90eed648 ("drm/i915: Split ilk vs. icl csc matrix handling") |
| b281264f8b81 ("drm/i915: Clean the csc limited range/identity programming") |
| c9e235aa0f9d ("drm/i915: Extract ilk_csc_convert_ctm()") |
| d2c19b06d6ea ("drm/i915: Clean up ilk/icl pipe/output CSC programming") |
| 386ba08fb595 ("drm/i915: Extract ilk_csc_limited_range()") |
| 9fdfb8e7308b ("drm/i915: Precompute/readout/check CHV CGM mode") |
| a1f1e61bfb0a ("drm/i915: Readout and check csc_mode") |
| 2dd24a9c2c8d ("drm/i915/gen11+: First assume next platforms will inherit stuff") |
| 37fbbd49054b ("drm/i915: Populate pipe_offsets[] & co. accurately") |
| 993298af26b1 ("drm/i915: Yet another if/else sort of newer to older platforms.") |
| e6ed078d6ddd ("drm/i915/icl: Add degamma and gamma lut size to gen11 caps") |
| a91de580541c ("drm/i915/icl: Enable pipe output csc") |
| 255fcfbc3c18 ("drm/i915/icl: Enable ICL Pipe CSC block") |
| 13717cef4c1d ("drm/i915/icl: Add icl pipe degamma and gamma support") |
| 8957129cb3b0 ("drm/i915/glk: Fix degamma lut programming") |
| 02c52f1ed20a ("drm/i915: Disable pipe gamma when C8 pixel format is used") |
| 0593d2cd3813 ("drm/i915: Turn off pipe CSC when it's not needed") |
| 0fc3f8e7540f ("drm/i915: Turn off pipe gamma when it's not needed") |
| 8271b2ef71aa ("drm/i915: Track pipe csc enable in crtc state") |
| 5f29ab23046a ("drm/i915: Track pipe gamma enable/disable in crtc state") |
| 9d5441de28e2 ("drm/i915: Populate gamma_mode for all platforms") |
| 051a6d8d3ca0 ("drm/i915: Move LUT programming to happen after vblank waits") |
| 4d8ed54c0447 ("drm/i915: Split color mgmt based on single vs. double buffered registers") |
| 87cefd57c88a ("drm/i915: Pull GAMMA_MODE write out from haswell_load_luts()") |
| 23b03a272c2b ("drm/i915: Constify the state arguments to the color management stuff") |
| 5f4f3e386b36 ("drm/i915: Precompute gamma_mode") |
| 7eb31a0bb2c1 ("drm/i915: Split the gamma/csc enable bits from the plane_ctl() function") |
| 108d14bdaef6 ("drm/i915: Setup PIPE_CHICKEN for fastsets too") |
| e4c0d5314ded ("drm/i915: Apply LUT validation checks to platforms more accurately (v3)") |
| c0550305fcbd ("drm/i915: Force background color to black for gen9+ (v2)") |
| 790cc9941b13 ("drm/i915: Clean up intel_plane_atomic_check_with_state()") |
| b3c316b0b869 ("drm/i915/icl: Define MOCS table for Icelake") |
