f7f38ffef56b ("drm/amd/display: fixup DPP programming sequence")
057fc695e934 ("drm/amd/display: support "dummy pstate"")
39bca3599aab ("drm/amd/display: add a option to force the clock at every mode change.")
290129c25617 ("drm/amd/display: Add CM_BYPASS via debug option")
70f1476a7eed ("drm/amd/display: Add debug option to disable timing sync")
6de202373bf6 ("drm/amd/display: move bw calc code into helpers")
93c25fbdc30a ("drm/amd/display: initialize p_state to proper value")
a6465d1f3b8f ("drm/amd/display: dcn2 use fixed clocks.")
6e17b5b8a846 ("drm/amd/display: update DCN2 uclk switch time")
2131f65581ba ("drm/amd/display: add support for forcing DCFCLK without affecting watermarks")
a746a2585542 ("drm/amd/display: Drive-by fixes for display_mode_vba")
ed07237c0c48 ("drm/amd/display: Fix LB BPP and Cursor width")
040a4d63bde4 ("drm/amd/display: DCHUB requestors numbers for Navi.")
42351c66aedc ("drm/amd/display: Add profiling tools for bandwidth validation")
254eb07cb090 ("drm/amd/display: Optimize bandwidth validation by adding early return")
776c1f569f94 ("drm/amd/display: Properly guard display_mode_vba with DCN2")
8e27a2d4cd76 ("drm/amd/display: Fix DCFCLK and SOCCLK not set")
b7d39c587877 ("drm/amd/display: move dsc clock from plane_resource to stream_resource")
0ba37b20ef1c ("drm/amd/display: fix dsc validation")
00999d991fde ("drm/amd/display: clean up validation failure log spam")
6ba117404e41 ("drm/amd/display: fix pstate allow handling in dcn2")
c69dd2d06cdf ("drm/amd/display: Refactor clk_mgr functions")
8712bda45cdc ("drm/amd/display: dcn2 dmcu wait_for_loop update with dispclk.")
97bda0322b8a ("drm/amd/display: Add DSC support for Navi (v2)")
476e955dd679 ("drm/amd/display: Hook DCN2 into amdgpu_dm and expose as config (v2)")
e249428256e2 ("drm/amd/display: updates for dcn20_update_bandwidth")
cb0b554abeac ("drm/amd/display: add fast_validate parameter to dcn20_validate_bandwidth")
6fbefb84a98e ("drm/amd/display: Add DC core changes for DCN2")
7ed4e6352c16 ("drm/amd/display: Add DCN2 HW Sequencer and Resource")
345429a67c48 ("drm/amd/display: Add DCN2 DWB")
bbeb64d0eb78 ("drm/amd/display: Add DCN2 HUBP and HUBBUB")
f7de96ee8b5f ("drm/amd/display: Add DCN2 DPP")
f789b0b82bf0 ("drm/amd/display: Add DCN2 MPC")
2d78b3a177fe ("drm/amd/display: Add DCN2 OPTC")
fcee01b9f82d ("drm/amd/display: Add DCN2 clk mgr")
ca4d9b3a5a3b ("drm/amd/display: Add DCN2 DIO")
728c06986a4f ("drm/amd/display: Add DCN2 changes to DML")
48321c3dde79 ("drm/amd/display: Read soc_bounding_box from gpu_info (v2)")
35c2e91059cb ("drm/amdgpu: parse the new members added by gpu_info ucode v1_1")
109c80ddb40f ("drm/amdgpu: add gpu_info_firmware v1_1 structure for navi10")
c5c07cb5435e ("drm/amd/display: Refactor DIO stream encoder")
baa1fd7f32f2 ("drm/amd/display: Refactor clk_mgr functions")
961ea20155d7 ("drm/amd/display: Fix type of pp_smu_wm_set_range struct")
8e0546d6c4b1 ("drm/amd/display: Add min_dcfclk_mhz field to bb overrides")
9b93eb475aa9 ("drm/amd/display: move clk_mgr files to right place")
e63e2491ad92 ("drm/amd/display: Ensure DRR triggers in BP")
313a9a21ff46 ("drm/amd/display: Add GSL source select registers")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
78cc70b1e47d ("drm/amd/display: Engine-specific encoder allocation")
6476a7c8f031 ("drm/amd/display: Program VTG params after programming Global Sync")