| 0d142232d943 ("drm/amdgpu: update golden setting for sienna_cichlid") |
| 263acd471f50 ("drm/amdgpu/gfx10: add gc golden setting for sienna_cichlid") |
| 58139a42dc08 ("drm/amdgpu/gfx10: change register configure for sienna_cichlid") |
| 933c8a93e241 ("drm/amdgpu: add gfx ip block for sienna_cichlid (v3)") |
| 757b3af8ecb4 ("drm/amdgpu: add ih ip block for sienna_cichlid") |
| 0b3df16b5abc ("drm/amdgpu: add gmc ip block for sienna_cichlid") |
| 2e1ba10e9271 ("drm/amdgpu/soc15: add common ip block for sienna_cichlid") |
| 43a10b15d442 ("amd/amdgpu: Limit rlcg write registers only for nv12") |
| b2d92682ff6a ("drm/amdgpu: add SPM golden settings for Navi12") |
| 1675c3a24d07 ("drm/amdgpu: stop disable the scheduler during HW fini") |
| 2e0cc4d48b91 ("drm/amdgpu: revise RLCG access path") |
| f091c1c70e89 ("drm/amdgpu: disable 3D pipe 1 on Navi1x") |
| 1da7d4a8ab79 ("drm/amdgpu: Write blocked CP registers using RLC on VF") |
| 460c484f2411 ("drm/amdgpu: Initialize SPM_VMID with 0xf (v2)") |
| 640f07932541 ("drm/amdgpu: Remove unneeded semicolon in gfx_v10_0.c") |
| a5e82d0b9505 ("drm/amdgpu/gfx10: unlock srbm_mutex after queue programming finish") |
| c25edaaf75af ("drm/amdgpu/gfx10: re-init clear state buffer after gpu reset") |
| 387d40fd6fb6 ("drm/amdgpu/gfx10: explicitly wait for cp idle after halt/unhalt") |
| 4effa8dbc117 ("drm/amdgpu/vcn2.5: fix the enc loop with hw fini") |
| 14f43e8f88c5 ("drm/amdgpu: move JPEG2.5 out from VCN2.5") |
| b0f3cd3191cd ("drm/amdgpu: remove unnecessary JPEG2.0 code from VCN2.0") |
| 6ac27241106b ("drm/amdgpu: add JPEG v2.0 function supports") |
| bb0db70f3f75 ("drm/amdgpu: separate JPEG1.0 code out from VCN1.0") |
| 9d9cc9b8fe85 ("drm/amdgpu: add amdgpu_jpeg and JPEG tests") |
| 88a1c40a04de ("drm/amdgpu: add JPEG HW IP and SW structures") |
| ad02e08e0578 ("drm/amdgpu: Report vram vendor with sysfs (v3)") |
| fd287c8cd248 ("drm/amdgpu/vcn: use amdgpu_ring_test_helper") |
| 631cdbd27e92 ("drm/amdgpu/atomfirmware: simplify the interface to get vram info") |
| bd5520273cea ("drm/amdgpu/atomfirmware: use proper index for querying vram type (v3)") |
| 393993ac0cc9 ("drm/amdgpu/SRIOV: Navi12 SRIOV VF gets GTT base") |
| 9d1b3c78052e ("drm/amdgpu: reserve at least 4MB of VRAM for page tables v2") |
| 3ff985485b29 ("drm/amdgpu: Export function to flush TLB of specific vm hub") |
| 244511f386cc ("drm/amdgpu: simplify and cleanup setting the dma mask") |
| f8984cb9e3e9 ("drm/amdgpu/gfx10: add golden settings for navi12 (v2)") |
| 44e9e7c96c5e ("drm/amdgpu: add ip blocks for navi12") |
| 9ff3dba6d68d ("drm/amdgpu/gfx10: set number of me(c)/pipe/queue for navi12") |
| 716e9bb099c5 ("drm/amdgpu/gfx10: add placeholder for navi12 golden settings") |
| 6983469c1a65 ("drm/amdgpu/gfx10: add gfx config for navi12") |
| 4cd4c5c064bd ("drm/amdgpu: cleanup vega10 SRIOV code path") |
| cd1fd7b3818a ("drm/amdgpu: add harvest support for Arcturus") |
| fa739f4b0686 ("drm/amdgpu: add multiple instances support for Arcturus") |
| c01b6a1d3867 ("drm/amdgpu: modify amdgpu_vcn to support multiple instances") |
| 989b6a054997 ("drm/amdgpu: add vcn nbio doorbell range setting for 2nd vcn instance") |
| 530e30fc32d3 ("drm/amdgpu: enable the Doorbell support for VCN2.5") |
| 39a5053fb223 ("drm/amdgpu: add vcn doorbell range function to nbio7.4 (v2)") |
| 800107370810 ("drm/amdgpu/VCN2.5: set JPEG decode ring functions") |
| e87d5a7a23c7 ("drm/amdgpu: add JPEG2.5 HW start and stop") |
| a4767886e5cb ("drm/amdgpu/VCN2.5: set encode ring functions") |
| 185a579700ec ("drm/amdgpu/VCN2.5: set decode ring functions") |
| cbead2bdfcf1 ("drm/amdgpu: add VCN2.5 VCPU start and stop") |
