| 1e8955fd832c ("PCI/ASPM: Pass L1SS Capabilities value, not struct aspm_register_info") |
| 80d7d7a904fa ("PCI/ASPM: Calculate LTR_L1.2_THRESHOLD from device characteristics") |
| a48f3d5b1974 ("PCI/ASPM: Add L1 Substates definitions") |
| 7f88ba4a19b9 ("PCI/ASPM: Reformat ASPM register definitions") |
| c00054f540bf ("PCI/ASPM: Use correct capability pointer to program LTR_L1.2_THRESHOLD") |
| 94ac327e043e ("PCI/ASPM: Account for downstream device's Port Common_Mode_Restore_Time") |
| aeda9adebab8 ("PCI/ASPM: Configure L1 substate settings") |
| f1f0366dd6be ("PCI/ASPM: Calculate and save the L1.2 timing parameters") |
| b5a0a9b59c81 ("PCI/ASPM: Read and set up L1 substate capabilities") |
| 0fc1223f0e77 ("PCI/ASPM: Add L1 substate capability structure register definitions") |
| e53f9a28bee3 ("PCI/ASPM: Don't retrain link if ASPM not possible") |
