| 008a4016c5cf ("drm/amd/display: Set FEC_READY always before link training") |
| e0a6440a2961 ("drm/amd/display: Add ability to set preferred link training parameters.") |
| 97bda0322b8a ("drm/amd/display: Add DSC support for Navi (v2)") |
| 476e955dd679 ("drm/amd/display: Hook DCN2 into amdgpu_dm and expose as config (v2)") |
| 6fbefb84a98e ("drm/amd/display: Add DC core changes for DCN2") |
| 7ed4e6352c16 ("drm/amd/display: Add DCN2 HW Sequencer and Resource") |
| 345429a67c48 ("drm/amd/display: Add DCN2 DWB") |
| 2d78b3a177fe ("drm/amd/display: Add DCN2 OPTC") |
| ca4d9b3a5a3b ("drm/amd/display: Add DCN2 DIO") |
| 48321c3dde79 ("drm/amd/display: Read soc_bounding_box from gpu_info (v2)") |
| 35c2e91059cb ("drm/amdgpu: parse the new members added by gpu_info ucode v1_1") |
| 109c80ddb40f ("drm/amdgpu: add gpu_info_firmware v1_1 structure for navi10") |
| ecbc382c9fdf ("Revert "drm/amd/display: Rework CRTC color management"") |
| f94ec6f8b885 ("Revert "drm/amd/display: move vmid determination logic out of dc"") |
| 76d981a9fe82 ("Revert "drm/amd/display: make clk_mgr call enable_pme_wa"") |
| a1651530a3ba ("drm/amd/display: make clk_mgr call enable_pme_wa") |
| 16b6253a0837 ("drm/amd/display: Do not grant POST_LT_ADJ when TPS4 is used") |
| 11cd74cdb98a ("drm/amd/display: move vmid determination logic out of dc") |
| 7cd4b70091a5 ("drm/amd/display: Rework CRTC color management") |
| c5c07cb5435e ("drm/amd/display: Refactor DIO stream encoder") |
| 961ea20155d7 ("drm/amd/display: Fix type of pp_smu_wm_set_range struct") |
| fe798de53a7a ("drm/amd/display: Move link functions from dc to dc_link") |
| e63e2491ad92 ("drm/amd/display: Ensure DRR triggers in BP") |
| 313a9a21ff46 ("drm/amd/display: Add GSL source select registers") |
| dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific") |
| 78cc70b1e47d ("drm/amd/display: Engine-specific encoder allocation") |
| eed928dcd83e ("drm/amd/display: enabling stream after HPD low to high happened") |
| 6476a7c8f031 ("drm/amd/display: Program VTG params after programming Global Sync") |
| 24c18794946a ("drm/amd/display: add null checks and set update flags") |
| 97df424fe7a7 ("drm/amd/display: Drop DCN1_01 guards") |
| d7316ddc610f ("drm/amd/display: Add ASICREV_IS_PICASSO") |
| 88ccdf1d59df ("drm/amd/display: Expose send immediate sdp message interface") |
| b2293ac23776 ("drm/amd/display: move back vbios cmd table for set dprefclk") |
| e7e10c464a48 ("drm/amd/display: stop external access to internal optc sync params") |
| db819940b0ef ("drm/amd/display: move signal type out of otg dlg params") |
| 21e471f0850d ("drm/amd/display: Set dispclk and dprefclock directly") |
| 09aef2c48e79 ("drm/amd/display: Compensate for pre-DCE12 BTR-VRR hw limitations. (v3)") |
| a0867053408e ("drm/amd/display: remove deprecated pplib interface") |
| 27eaa4927dc3 ("drm/amd/display: Add power down display on boot flag") |
| d6ef9b4175e8 ("drm/amd/display: Refactor CRTC interrupt toggling logic") |
| f55be0be5b72 ("drm/amd/display: Add profiling tools for bandwidth validation") |
| afcd526b1ba9 ("drm/amd/display: Add fast_validate parameter") |
| c14a005c1621 ("drm/amd/display: Relax requirements for CRTCs to be enabled") |
| 5ac4619b9d2f ("drm/amd/display: change name from dc_link_get_verified_link_cap to dc_link_get_link_cap") |
| 695af5f9a519 ("drm/amd/display: Rework DC plane filling and surface updates") |
| 320932bfd9e3 ("drm/amd/display: Recalculate pitch when buffers change") |
| 781718322779 ("drm/amd/display: Update plane scaling parameters for fast updates") |
| c7e557ab46a7 ("drm/amd/display: Clean up locking in dcn*_apply_ctx_for_surface()") |
| c85fc65e2241 ("drm/amd/display: init dc_config before rest of DC init") |
| 004fefa385b4 ("drm/amd/display: Set surface color space from DRM plane state") |
