drm/i915: Add CxSR support on Pineview DDR3
BugLink: http://bugs.launchpad.net/bugs/1004707
Pineview with DDR3 memory has different latencies to enable CxSR.
This patch updates CxSR latency table to add Pineview DDR3 latency
configuration. It also adds one flag "is_ddr3" for checking DDR3
setting in MCHBAR.
Cc: Shaohua Li <shaohua.li@intel.com>
Cc: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Li Peng <peng.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 9553426372eef71c849499fb1d232f4b0577c0f9)
Signed-off-by: Chris J Arges <chris.j.arges@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>
4 files changed
