| /******************************************************************************* |
| This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. |
| ST Ethernet IPs are built around a Synopsys IP Core. |
| |
| Copyright(C) 2007-2011 STMicroelectronics Ltd |
| |
| This program is free software; you can redistribute it and/or modify it |
| under the terms and conditions of the GNU General Public License, |
| version 2, as published by the Free Software Foundation. |
| |
| This program is distributed in the hope it will be useful, but WITHOUT |
| ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| more details. |
| |
| The full GNU General Public License is included in this distribution in |
| the file called "COPYING". |
| |
| Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> |
| |
| Documentation available at: |
| http://www.stlinux.com |
| Support available at: |
| https://bugzilla.stlinux.com/ |
| *******************************************************************************/ |
| |
| #include <linux/clk.h> |
| #include <linux/kernel.h> |
| #include <linux/interrupt.h> |
| #include <linux/ip.h> |
| #include <linux/tcp.h> |
| #include <linux/skbuff.h> |
| #include <linux/ethtool.h> |
| #include <linux/if_ether.h> |
| #include <linux/crc32.h> |
| #include <linux/mii.h> |
| #include <linux/if.h> |
| #include <linux/if_vlan.h> |
| #include <linux/dma-mapping.h> |
| #include <linux/slab.h> |
| #include <linux/prefetch.h> |
| #include <linux/pinctrl/consumer.h> |
| #ifdef CONFIG_DEBUG_FS |
| #include <linux/debugfs.h> |
| #include <linux/seq_file.h> |
| #endif /* CONFIG_DEBUG_FS */ |
| #include <linux/net_tstamp.h> |
| #include "stmmac_ptp.h" |
| #include "stmmac.h" |
| #include <linux/reset.h> |
| #include <linux/of_mdio.h> |
| #include "dwmac1000.h" |
| |
| #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) |
| #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) |
| |
| /* Module parameters */ |
| #define TX_TIMEO 5000 |
| static int watchdog = TX_TIMEO; |
| module_param(watchdog, int, S_IRUGO | S_IWUSR); |
| MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); |
| |
| static int debug = -1; |
| module_param(debug, int, S_IRUGO | S_IWUSR); |
| MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); |
| |
| static int phyaddr = -1; |
| module_param(phyaddr, int, S_IRUGO); |
| MODULE_PARM_DESC(phyaddr, "Physical device address"); |
| |
| #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4) |
| #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4) |
| |
| static int flow_ctrl = FLOW_OFF; |
| module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); |
| MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); |
| |
| static int pause = PAUSE_TIME; |
| module_param(pause, int, S_IRUGO | S_IWUSR); |
| MODULE_PARM_DESC(pause, "Flow Control Pause Time"); |
| |
| #define TC_DEFAULT 64 |
| static int tc = TC_DEFAULT; |
| module_param(tc, int, S_IRUGO | S_IWUSR); |
| MODULE_PARM_DESC(tc, "DMA threshold control value"); |
| |
| #define DEFAULT_BUFSIZE 1536 |
| static int buf_sz = DEFAULT_BUFSIZE; |
| module_param(buf_sz, int, S_IRUGO | S_IWUSR); |
| MODULE_PARM_DESC(buf_sz, "DMA buffer size"); |
| |
| #define STMMAC_RX_COPYBREAK 256 |
| |
| static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
| NETIF_MSG_LINK | NETIF_MSG_IFUP | |
| NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); |
| |
| #define STMMAC_DEFAULT_LPI_TIMER 1000 |
| static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; |
| module_param(eee_timer, int, S_IRUGO | S_IWUSR); |
| MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); |
| #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) |
| |
| /* By default the driver will use the ring mode to manage tx and rx descriptors, |
| * but allow user to force to use the chain instead of the ring |
| */ |
| static unsigned int chain_mode; |
| module_param(chain_mode, int, S_IRUGO); |
| MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); |
| |
| static irqreturn_t stmmac_interrupt(int irq, void *dev_id); |
| |
| #ifdef CONFIG_DEBUG_FS |
| static int stmmac_init_fs(struct net_device *dev); |
| static void stmmac_exit_fs(struct net_device *dev); |
| #endif |
| |
| #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) |
| |
| /** |
| * stmmac_verify_args - verify the driver parameters. |
| * Description: it checks the driver parameters and set a default in case of |
| * errors. |
| */ |
| static void stmmac_verify_args(void) |
| { |
| if (unlikely(watchdog < 0)) |
| watchdog = TX_TIMEO; |
| if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) |
| buf_sz = DEFAULT_BUFSIZE; |
| if (unlikely(flow_ctrl > 1)) |
| flow_ctrl = FLOW_AUTO; |
| else if (likely(flow_ctrl < 0)) |
| flow_ctrl = FLOW_OFF; |
| if (unlikely((pause < 0) || (pause > 0xffff))) |
| pause = PAUSE_TIME; |
| if (eee_timer < 0) |
| eee_timer = STMMAC_DEFAULT_LPI_TIMER; |
| } |
| |
| /** |
| * stmmac_disable_all_queues - Disable all queues |
| * @priv: driver private structure |
| */ |
| static void stmmac_disable_all_queues(struct stmmac_priv *priv) |
| { |
| u32 rx_queues_cnt = priv->plat->rx_queues_to_use; |
| u32 queue; |
| |
| for (queue = 0; queue < rx_queues_cnt; queue++) { |
| struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; |
| |
| napi_disable(&rx_q->napi); |
| } |
| } |
| |
| /** |
| * stmmac_enable_all_queues - Enable all queues |
| * @priv: driver private structure |
| */ |
| static void stmmac_enable_all_queues(struct stmmac_priv *priv) |
| { |
| u32 rx_queues_cnt = priv->plat->rx_queues_to_use; |
| u32 queue; |
| |
| for (queue = 0; queue < rx_queues_cnt; queue++) { |
| struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; |
| |
| napi_enable(&rx_q->napi); |
| } |
| } |
| |
| /** |
| * stmmac_stop_all_queues - Stop all queues |
| * @priv: driver private structure |
| */ |
| static void stmmac_stop_all_queues(struct stmmac_priv *priv) |
| { |
| u32 tx_queues_cnt = priv->plat->tx_queues_to_use; |
| u32 queue; |
| |
| for (queue = 0; queue < tx_queues_cnt; queue++) |
| netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); |
| } |
| |
| /** |
| * stmmac_start_all_queues - Start all queues |
| * @priv: driver private structure |
| */ |
| static void stmmac_start_all_queues(struct stmmac_priv *priv) |
| { |
| u32 tx_queues_cnt = priv->plat->tx_queues_to_use; |
| u32 queue; |
| |
| for (queue = 0; queue < tx_queues_cnt; queue++) |
| netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue)); |
| } |
| |
| /** |
| * stmmac_clk_csr_set - dynamically set the MDC clock |
| * @priv: driver private structure |
| * Description: this is to dynamically set the MDC clock according to the csr |
| * clock input. |
| * Note: |
| * If a specific clk_csr value is passed from the platform |
| * this means that the CSR Clock Range selection cannot be |
| * changed at run-time and it is fixed (as reported in the driver |
| * documentation). Viceversa the driver will try to set the MDC |
| * clock dynamically according to the actual clock input. |
| */ |
| static void stmmac_clk_csr_set(struct stmmac_priv *priv) |
| { |
| u32 clk_rate; |
| |
| clk_rate = clk_get_rate(priv->plat->stmmac_clk); |
| |
| /* Platform provided default clk_csr would be assumed valid |
| * for all other cases except for the below mentioned ones. |
| * For values higher than the IEEE 802.3 specified frequency |
| * we can not estimate the proper divider as it is not known |
| * the frequency of clk_csr_i. So we do not change the default |
| * divider. |
| */ |
| if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { |
| if (clk_rate < CSR_F_35M) |
| priv->clk_csr = STMMAC_CSR_20_35M; |
| else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) |
| priv->clk_csr = STMMAC_CSR_35_60M; |
| else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) |
| priv->clk_csr = STMMAC_CSR_60_100M; |
| else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) |
| priv->clk_csr = STMMAC_CSR_100_150M; |
| else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) |
| priv->clk_csr = STMMAC_CSR_150_250M; |
| else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) |
| priv->clk_csr = STMMAC_CSR_250_300M; |
| } |
| } |
| |
| static void print_pkt(unsigned char *buf, int len) |
| { |
| pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); |
| print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); |
| } |
| |
| static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) |
| { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; |
| u32 avail; |
| |
| if (tx_q->dirty_tx > tx_q->cur_tx) |
| avail = tx_q->dirty_tx - tx_q->cur_tx - 1; |
| else |
| avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1; |
| |
| return avail; |
| } |
| |
| /** |
| * stmmac_rx_dirty - Get RX queue dirty |
| * @priv: driver private structure |
| * @queue: RX queue index |
| */ |
| static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) |
| { |
| struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; |
| u32 dirty; |
| |
| if (rx_q->dirty_rx <= rx_q->cur_rx) |
| dirty = rx_q->cur_rx - rx_q->dirty_rx; |
| else |
| dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx; |
| |
| return dirty; |
| } |
| |
| /** |
| * stmmac_hw_fix_mac_speed - callback for speed selection |
| * @priv: driver private structure |
| * Description: on some platforms (e.g. ST), some HW system configuration |
| * registers have to be set according to the link speed negotiated. |
| */ |
| static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) |
| { |
| struct net_device *ndev = priv->dev; |
| struct phy_device *phydev = ndev->phydev; |
| |
| if (likely(priv->plat->fix_mac_speed)) |
| priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed); |
| } |
| |
| /** |
| * stmmac_enable_eee_mode - check and enter in LPI mode |
| * @priv: driver private structure |
| * Description: this function is to verify and enter in LPI mode in case of |
| * EEE. |
| */ |
| static void stmmac_enable_eee_mode(struct stmmac_priv *priv) |
| { |
| u32 tx_cnt = priv->plat->tx_queues_to_use; |
| u32 queue; |
| |
| /* check if all TX queues have the work finished */ |
| for (queue = 0; queue < tx_cnt; queue++) { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; |
| |
| if (tx_q->dirty_tx != tx_q->cur_tx) |
| return; /* still unfinished work */ |
| } |
| |
| /* Check and enter in LPI mode */ |
| if (!priv->tx_path_in_lpi_mode) |
| priv->hw->mac->set_eee_mode(priv->hw, |
| priv->plat->en_tx_lpi_clockgating); |
| } |
| |
| /** |
| * stmmac_disable_eee_mode - disable and exit from LPI mode |
| * @priv: driver private structure |
| * Description: this function is to exit and disable EEE in case of |
| * LPI state is true. This is called by the xmit. |
| */ |
| void stmmac_disable_eee_mode(struct stmmac_priv *priv) |
| { |
| priv->hw->mac->reset_eee_mode(priv->hw); |
| del_timer_sync(&priv->eee_ctrl_timer); |
| priv->tx_path_in_lpi_mode = false; |
| } |
| |
| /** |
| * stmmac_eee_ctrl_timer - EEE TX SW timer. |
| * @arg : data hook |
| * Description: |
| * if there is no data transfer and if we are not in LPI state, |
| * then MAC Transmitter can be moved to LPI state. |
| */ |
| static void stmmac_eee_ctrl_timer(unsigned long arg) |
| { |
| struct stmmac_priv *priv = (struct stmmac_priv *)arg; |
| |
| stmmac_enable_eee_mode(priv); |
| mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); |
| } |
| |
| /** |
| * stmmac_eee_init - init EEE |
| * @priv: driver private structure |
| * Description: |
| * if the GMAC supports the EEE (from the HW cap reg) and the phy device |
| * can also manage EEE, this function enable the LPI state and start related |
| * timer. |
| */ |
| bool stmmac_eee_init(struct stmmac_priv *priv) |
| { |
| struct net_device *ndev = priv->dev; |
| unsigned long flags; |
| bool ret = false; |
| |
| /* Using PCS we cannot dial with the phy registers at this stage |
| * so we do not support extra feature like EEE. |
| */ |
| if ((priv->hw->pcs == STMMAC_PCS_RGMII) || |
| (priv->hw->pcs == STMMAC_PCS_TBI) || |
| (priv->hw->pcs == STMMAC_PCS_RTBI)) |
| goto out; |
| |
| /* MAC core supports the EEE feature. */ |
| if (priv->dma_cap.eee) { |
| int tx_lpi_timer = priv->tx_lpi_timer; |
| |
| /* Check if the PHY supports EEE */ |
| if (phy_init_eee(ndev->phydev, 1)) { |
| /* To manage at run-time if the EEE cannot be supported |
| * anymore (for example because the lp caps have been |
| * changed). |
| * In that case the driver disable own timers. |
| */ |
| spin_lock_irqsave(&priv->lock, flags); |
| if (priv->eee_active) { |
| netdev_dbg(priv->dev, "disable EEE\n"); |
| del_timer_sync(&priv->eee_ctrl_timer); |
| priv->hw->mac->set_eee_timer(priv->hw, 0, |
| tx_lpi_timer); |
| } |
| priv->eee_active = 0; |
| spin_unlock_irqrestore(&priv->lock, flags); |
| goto out; |
| } |
| /* Activate the EEE and start timers */ |
| spin_lock_irqsave(&priv->lock, flags); |
| if (!priv->eee_active) { |
| priv->eee_active = 1; |
| setup_timer(&priv->eee_ctrl_timer, |
| stmmac_eee_ctrl_timer, |
| (unsigned long)priv); |
| mod_timer(&priv->eee_ctrl_timer, |
| STMMAC_LPI_T(eee_timer)); |
| |
| priv->hw->mac->set_eee_timer(priv->hw, |
| STMMAC_DEFAULT_LIT_LS, |
| tx_lpi_timer); |
| } |
| /* Set HW EEE according to the speed */ |
| priv->hw->mac->set_eee_pls(priv->hw, ndev->phydev->link); |
| |
| ret = true; |
| spin_unlock_irqrestore(&priv->lock, flags); |
| |
| netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); |
| } |
| out: |
| return ret; |
| } |
| |
| /* stmmac_get_tx_hwtstamp - get HW TX timestamps |
| * @priv: driver private structure |
| * @p : descriptor pointer |
| * @skb : the socket buffer |
| * Description : |
| * This function will read timestamp from the descriptor & pass it to stack. |
| * and also perform some sanity checks. |
| */ |
| static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, |
| struct dma_desc *p, struct sk_buff *skb) |
| { |
| struct skb_shared_hwtstamps shhwtstamp; |
| u64 ns; |
| |
| if (!priv->hwts_tx_en) |
| return; |
| |
| /* exit if skb doesn't support hw tstamp */ |
| if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) |
| return; |
| |
| /* check tx tstamp status */ |
| if (!priv->hw->desc->get_tx_timestamp_status(p)) { |
| /* get the valid tstamp */ |
| ns = priv->hw->desc->get_timestamp(p, priv->adv_ts); |
| |
| memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); |
| shhwtstamp.hwtstamp = ns_to_ktime(ns); |
| |
| netdev_info(priv->dev, "get valid TX hw timestamp %llu\n", ns); |
| /* pass tstamp to stack */ |
| skb_tstamp_tx(skb, &shhwtstamp); |
| } |
| |
| return; |
| } |
| |
| /* stmmac_get_rx_hwtstamp - get HW RX timestamps |
| * @priv: driver private structure |
| * @p : descriptor pointer |
| * @np : next descriptor pointer |
| * @skb : the socket buffer |
| * Description : |
| * This function will read received packet's timestamp from the descriptor |
| * and pass it to stack. It also perform some sanity checks. |
| */ |
| static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, |
| struct dma_desc *np, struct sk_buff *skb) |
| { |
| struct skb_shared_hwtstamps *shhwtstamp = NULL; |
| u64 ns; |
| |
| if (!priv->hwts_rx_en) |
| return; |
| |
| /* Check if timestamp is available */ |
| if (!priv->hw->desc->get_rx_timestamp_status(p, priv->adv_ts)) { |
| /* For GMAC4, the valid timestamp is from CTX next desc. */ |
| if (priv->plat->has_gmac4) |
| ns = priv->hw->desc->get_timestamp(np, priv->adv_ts); |
| else |
| ns = priv->hw->desc->get_timestamp(p, priv->adv_ts); |
| |
| netdev_info(priv->dev, "get valid RX hw timestamp %llu\n", ns); |
| shhwtstamp = skb_hwtstamps(skb); |
| memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); |
| shhwtstamp->hwtstamp = ns_to_ktime(ns); |
| } else { |
| netdev_err(priv->dev, "cannot get RX hw timestamp\n"); |
| } |
| } |
| |
| /** |
| * stmmac_hwtstamp_ioctl - control hardware timestamping. |
| * @dev: device pointer. |
| * @ifr: An IOCTL specific structure, that can contain a pointer to |
| * a proprietary structure used to pass information to the driver. |
| * Description: |
| * This function configures the MAC to enable/disable both outgoing(TX) |
| * and incoming(RX) packets time stamping based on user input. |
| * Return Value: |
| * 0 on success and an appropriate -ve integer on failure. |
| */ |
| static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) |
| { |
| struct stmmac_priv *priv = netdev_priv(dev); |
| struct hwtstamp_config config; |
| struct timespec64 now; |
| u64 temp = 0; |
| u32 ptp_v2 = 0; |
| u32 tstamp_all = 0; |
| u32 ptp_over_ipv4_udp = 0; |
| u32 ptp_over_ipv6_udp = 0; |
| u32 ptp_over_ethernet = 0; |
| u32 snap_type_sel = 0; |
| u32 ts_master_en = 0; |
| u32 ts_event_en = 0; |
| u32 value = 0; |
| u32 sec_inc; |
| |
| if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { |
| netdev_alert(priv->dev, "No support for HW time stamping\n"); |
| priv->hwts_tx_en = 0; |
| priv->hwts_rx_en = 0; |
| |
| return -EOPNOTSUPP; |
| } |
| |
| if (copy_from_user(&config, ifr->ifr_data, |
| sizeof(struct hwtstamp_config))) |
| return -EFAULT; |
| |
| netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", |
| __func__, config.flags, config.tx_type, config.rx_filter); |
| |
| /* reserved for future extensions */ |
| if (config.flags) |
| return -EINVAL; |
| |
| if (config.tx_type != HWTSTAMP_TX_OFF && |
| config.tx_type != HWTSTAMP_TX_ON) |
| return -ERANGE; |
| |
| if (priv->adv_ts) { |
| switch (config.rx_filter) { |
| case HWTSTAMP_FILTER_NONE: |
| /* time stamp no incoming packet at all */ |
| config.rx_filter = HWTSTAMP_FILTER_NONE; |
| break; |
| |
| case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: |
| /* PTP v1, UDP, any kind of event packet */ |
| config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; |
| /* take time stamp for all event messages */ |
| snap_type_sel = PTP_TCR_SNAPTYPSEL_1; |
| |
| ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; |
| ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; |
| break; |
| |
| case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
| /* PTP v1, UDP, Sync packet */ |
| config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; |
| /* take time stamp for SYNC messages only */ |
| ts_event_en = PTP_TCR_TSEVNTENA; |
| |
| ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; |
| ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; |
| break; |
| |
| case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: |
| /* PTP v1, UDP, Delay_req packet */ |
| config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; |
| /* take time stamp for Delay_Req messages only */ |
| ts_master_en = PTP_TCR_TSMSTRENA; |
| ts_event_en = PTP_TCR_TSEVNTENA; |
| |
| ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; |
| ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; |
| break; |
| |
| case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: |
| /* PTP v2, UDP, any kind of event packet */ |
| config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; |
| ptp_v2 = PTP_TCR_TSVER2ENA; |
| /* take time stamp for all event messages */ |
| snap_type_sel = PTP_TCR_SNAPTYPSEL_1; |
| |
| ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; |
| ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; |
| break; |
| |
| case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: |
| /* PTP v2, UDP, Sync packet */ |
| config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; |
| ptp_v2 = PTP_TCR_TSVER2ENA; |
| /* take time stamp for SYNC messages only */ |
| ts_event_en = PTP_TCR_TSEVNTENA; |
| |
| ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; |
| ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; |
| break; |
| |
| case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: |
| /* PTP v2, UDP, Delay_req packet */ |
| config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; |
| ptp_v2 = PTP_TCR_TSVER2ENA; |
| /* take time stamp for Delay_Req messages only */ |
| ts_master_en = PTP_TCR_TSMSTRENA; |
| ts_event_en = PTP_TCR_TSEVNTENA; |
| |
| ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; |
| ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; |
| break; |
| |
| case HWTSTAMP_FILTER_PTP_V2_EVENT: |
| /* PTP v2/802.AS1 any layer, any kind of event packet */ |
| config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; |
| ptp_v2 = PTP_TCR_TSVER2ENA; |
| /* take time stamp for all event messages */ |
| snap_type_sel = PTP_TCR_SNAPTYPSEL_1; |
| |
| ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; |
| ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; |
| ptp_over_ethernet = PTP_TCR_TSIPENA; |
| break; |
| |
| case HWTSTAMP_FILTER_PTP_V2_SYNC: |
| /* PTP v2/802.AS1, any layer, Sync packet */ |
| config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; |
| ptp_v2 = PTP_TCR_TSVER2ENA; |
| /* take time stamp for SYNC messages only */ |
| ts_event_en = PTP_TCR_TSEVNTENA; |
| |
| ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; |
| ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; |
| ptp_over_ethernet = PTP_TCR_TSIPENA; |
| break; |
| |
| case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
| /* PTP v2/802.AS1, any layer, Delay_req packet */ |
| config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; |
| ptp_v2 = PTP_TCR_TSVER2ENA; |
| /* take time stamp for Delay_Req messages only */ |
| ts_master_en = PTP_TCR_TSMSTRENA; |
| ts_event_en = PTP_TCR_TSEVNTENA; |
| |
| ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; |
| ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; |
| ptp_over_ethernet = PTP_TCR_TSIPENA; |
| break; |
| |
| case HWTSTAMP_FILTER_ALL: |
| /* time stamp any incoming packet */ |
| config.rx_filter = HWTSTAMP_FILTER_ALL; |
| tstamp_all = PTP_TCR_TSENALL; |
| break; |
| |
| default: |
| return -ERANGE; |
| } |
| } else { |
| switch (config.rx_filter) { |
| case HWTSTAMP_FILTER_NONE: |
| config.rx_filter = HWTSTAMP_FILTER_NONE; |
| break; |
| default: |
| /* PTP v1, UDP, any kind of event packet */ |
| config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; |
| break; |
| } |
| } |
| priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); |
| priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; |
| |
| if (!priv->hwts_tx_en && !priv->hwts_rx_en) |
| priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, 0); |
| else { |
| value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | |
| tstamp_all | ptp_v2 | ptp_over_ethernet | |
| ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | |
| ts_master_en | snap_type_sel); |
| priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, value); |
| |
| /* program Sub Second Increment reg */ |
| sec_inc = priv->hw->ptp->config_sub_second_increment( |
| priv->ptpaddr, priv->plat->clk_ptp_rate, |
| priv->plat->has_gmac4); |
| temp = div_u64(1000000000ULL, sec_inc); |
| |
| /* calculate default added value: |
| * formula is : |
| * addend = (2^32)/freq_div_ratio; |
| * where, freq_div_ratio = 1e9ns/sec_inc |
| */ |
| temp = (u64)(temp << 32); |
| priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); |
| priv->hw->ptp->config_addend(priv->ptpaddr, |
| priv->default_addend); |
| |
| /* initialize system time */ |
| ktime_get_real_ts64(&now); |
| |
| /* lower 32 bits of tv_sec are safe until y2106 */ |
| priv->hw->ptp->init_systime(priv->ptpaddr, (u32)now.tv_sec, |
| now.tv_nsec); |
| } |
| |
| return copy_to_user(ifr->ifr_data, &config, |
| sizeof(struct hwtstamp_config)) ? -EFAULT : 0; |
| } |
| |
| /** |
| * stmmac_init_ptp - init PTP |
| * @priv: driver private structure |
| * Description: this is to verify if the HW supports the PTPv1 or PTPv2. |
| * This is done by looking at the HW cap. register. |
| * This function also registers the ptp driver. |
| */ |
| static int stmmac_init_ptp(struct stmmac_priv *priv) |
| { |
| if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) |
| return -EOPNOTSUPP; |
| |
| priv->adv_ts = 0; |
| /* Check if adv_ts can be enabled for dwmac 4.x core */ |
| if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp) |
| priv->adv_ts = 1; |
| /* Dwmac 3.x core with extend_desc can support adv_ts */ |
| else if (priv->extend_desc && priv->dma_cap.atime_stamp) |
| priv->adv_ts = 1; |
| |
| if (priv->dma_cap.time_stamp) |
| netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); |
| |
| if (priv->adv_ts) |
| netdev_info(priv->dev, |
| "IEEE 1588-2008 Advanced Timestamp supported\n"); |
| |
| priv->hw->ptp = &stmmac_ptp; |
| priv->hwts_tx_en = 0; |
| priv->hwts_rx_en = 0; |
| |
| stmmac_ptp_register(priv); |
| |
| return 0; |
| } |
| |
| static void stmmac_release_ptp(struct stmmac_priv *priv) |
| { |
| if (priv->plat->clk_ptp_ref) |
| clk_disable_unprepare(priv->plat->clk_ptp_ref); |
| stmmac_ptp_unregister(priv); |
| } |
| |
| /** |
| * stmmac_mac_flow_ctrl - Configure flow control in all queues |
| * @priv: driver private structure |
| * Description: It is used for configuring the flow control in all queues |
| */ |
| static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) |
| { |
| u32 tx_cnt = priv->plat->tx_queues_to_use; |
| |
| priv->hw->mac->flow_ctrl(priv->hw, duplex, priv->flow_ctrl, |
| priv->pause, tx_cnt); |
| } |
| |
| /** |
| * stmmac_adjust_link - adjusts the link parameters |
| * @dev: net device structure |
| * Description: this is the helper called by the physical abstraction layer |
| * drivers to communicate the phy link status. According the speed and duplex |
| * this driver can invoke registered glue-logic as well. |
| * It also invoke the eee initialization because it could happen when switch |
| * on different networks (that are eee capable). |
| */ |
| static void stmmac_adjust_link(struct net_device *dev) |
| { |
| struct stmmac_priv *priv = netdev_priv(dev); |
| struct phy_device *phydev = dev->phydev; |
| unsigned long flags; |
| int new_state = 0; |
| |
| if (!phydev) |
| return; |
| |
| spin_lock_irqsave(&priv->lock, flags); |
| |
| if (phydev->link) { |
| u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); |
| |
| /* Now we make sure that we can be in full duplex mode. |
| * If not, we operate in half-duplex mode. */ |
| if (phydev->duplex != priv->oldduplex) { |
| new_state = 1; |
| if (!(phydev->duplex)) |
| ctrl &= ~priv->hw->link.duplex; |
| else |
| ctrl |= priv->hw->link.duplex; |
| priv->oldduplex = phydev->duplex; |
| } |
| /* Flow Control operation */ |
| if (phydev->pause) |
| stmmac_mac_flow_ctrl(priv, phydev->duplex); |
| |
| if (phydev->speed != priv->speed) { |
| new_state = 1; |
| switch (phydev->speed) { |
| case 1000: |
| if (priv->plat->has_gmac || |
| priv->plat->has_gmac4) |
| ctrl &= ~priv->hw->link.port; |
| break; |
| case 100: |
| if (priv->plat->has_gmac || |
| priv->plat->has_gmac4) { |
| ctrl |= priv->hw->link.port; |
| ctrl |= priv->hw->link.speed; |
| } else { |
| ctrl &= ~priv->hw->link.port; |
| } |
| break; |
| case 10: |
| if (priv->plat->has_gmac || |
| priv->plat->has_gmac4) { |
| ctrl |= priv->hw->link.port; |
| ctrl &= ~(priv->hw->link.speed); |
| } else { |
| ctrl &= ~priv->hw->link.port; |
| } |
| break; |
| default: |
| netif_warn(priv, link, priv->dev, |
| "broken speed: %d\n", phydev->speed); |
| phydev->speed = SPEED_UNKNOWN; |
| break; |
| } |
| if (phydev->speed != SPEED_UNKNOWN) |
| stmmac_hw_fix_mac_speed(priv); |
| priv->speed = phydev->speed; |
| } |
| |
| writel(ctrl, priv->ioaddr + MAC_CTRL_REG); |
| |
| if (!priv->oldlink) { |
| new_state = 1; |
| priv->oldlink = 1; |
| } |
| } else if (priv->oldlink) { |
| new_state = 1; |
| priv->oldlink = 0; |
| priv->speed = SPEED_UNKNOWN; |
| priv->oldduplex = DUPLEX_UNKNOWN; |
| } |
| |
| if (new_state && netif_msg_link(priv)) |
| phy_print_status(phydev); |
| |
| spin_unlock_irqrestore(&priv->lock, flags); |
| |
| if (phydev->is_pseudo_fixed_link) |
| /* Stop PHY layer to call the hook to adjust the link in case |
| * of a switch is attached to the stmmac driver. |
| */ |
| phydev->irq = PHY_IGNORE_INTERRUPT; |
| else |
| /* At this stage, init the EEE if supported. |
| * Never called in case of fixed_link. |
| */ |
| priv->eee_enabled = stmmac_eee_init(priv); |
| } |
| |
| /** |
| * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported |
| * @priv: driver private structure |
| * Description: this is to verify if the HW supports the PCS. |
| * Physical Coding Sublayer (PCS) interface that can be used when the MAC is |
| * configured for the TBI, RTBI, or SGMII PHY interface. |
| */ |
| static void stmmac_check_pcs_mode(struct stmmac_priv *priv) |
| { |
| int interface = priv->plat->interface; |
| |
| if (priv->dma_cap.pcs) { |
| if ((interface == PHY_INTERFACE_MODE_RGMII) || |
| (interface == PHY_INTERFACE_MODE_RGMII_ID) || |
| (interface == PHY_INTERFACE_MODE_RGMII_RXID) || |
| (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { |
| netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); |
| priv->hw->pcs = STMMAC_PCS_RGMII; |
| } else if (interface == PHY_INTERFACE_MODE_SGMII) { |
| netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); |
| priv->hw->pcs = STMMAC_PCS_SGMII; |
| } |
| } |
| } |
| |
| /** |
| * stmmac_init_phy - PHY initialization |
| * @dev: net device structure |
| * Description: it initializes the driver's PHY state, and attaches the PHY |
| * to the mac driver. |
| * Return value: |
| * 0 on success |
| */ |
| static int stmmac_init_phy(struct net_device *dev) |
| { |
| struct stmmac_priv *priv = netdev_priv(dev); |
| struct phy_device *phydev; |
| char phy_id_fmt[MII_BUS_ID_SIZE + 3]; |
| char bus_id[MII_BUS_ID_SIZE]; |
| int interface = priv->plat->interface; |
| int max_speed = priv->plat->max_speed; |
| priv->oldlink = 0; |
| priv->speed = SPEED_UNKNOWN; |
| priv->oldduplex = DUPLEX_UNKNOWN; |
| |
| if (priv->plat->phy_node) { |
| phydev = of_phy_connect(dev, priv->plat->phy_node, |
| &stmmac_adjust_link, 0, interface); |
| } else { |
| snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", |
| priv->plat->bus_id); |
| |
| snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, |
| priv->plat->phy_addr); |
| netdev_dbg(priv->dev, "%s: trying to attach to %s\n", __func__, |
| phy_id_fmt); |
| |
| phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, |
| interface); |
| } |
| |
| if (IS_ERR_OR_NULL(phydev)) { |
| netdev_err(priv->dev, "Could not attach to PHY\n"); |
| if (!phydev) |
| return -ENODEV; |
| |
| return PTR_ERR(phydev); |
| } |
| |
| /* Stop Advertising 1000BASE Capability if interface is not GMII */ |
| if ((interface == PHY_INTERFACE_MODE_MII) || |
| (interface == PHY_INTERFACE_MODE_RMII) || |
| (max_speed < 1000 && max_speed > 0)) |
| phydev->advertising &= ~(SUPPORTED_1000baseT_Half | |
| SUPPORTED_1000baseT_Full); |
| |
| /* |
| * Broken HW is sometimes missing the pull-up resistor on the |
| * MDIO line, which results in reads to non-existent devices returning |
| * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent |
| * device as well. |
| * Note: phydev->phy_id is the result of reading the UID PHY registers. |
| */ |
| if (!priv->plat->phy_node && phydev->phy_id == 0) { |
| phy_disconnect(phydev); |
| return -ENODEV; |
| } |
| |
| /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid |
| * subsequent PHY polling, make sure we force a link transition if |
| * we have a UP/DOWN/UP transition |
| */ |
| if (phydev->is_pseudo_fixed_link) |
| phydev->irq = PHY_POLL; |
| |
| phy_attached_info(phydev); |
| return 0; |
| } |
| |
| static void stmmac_display_rx_rings(struct stmmac_priv *priv) |
| { |
| u32 rx_cnt = priv->plat->rx_queues_to_use; |
| void *head_rx; |
| u32 queue; |
| |
| /* Display RX rings */ |
| for (queue = 0; queue < rx_cnt; queue++) { |
| struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; |
| |
| pr_info("\tRX Queue %u rings\n", queue); |
| |
| if (priv->extend_desc) |
| head_rx = (void *)rx_q->dma_erx; |
| else |
| head_rx = (void *)rx_q->dma_rx; |
| |
| /* Display RX ring */ |
| priv->hw->desc->display_ring(head_rx, DMA_RX_SIZE, true); |
| } |
| } |
| |
| static void stmmac_display_tx_rings(struct stmmac_priv *priv) |
| { |
| u32 tx_cnt = priv->plat->tx_queues_to_use; |
| void *head_tx; |
| u32 queue; |
| |
| /* Display TX rings */ |
| for (queue = 0; queue < tx_cnt; queue++) { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; |
| |
| pr_info("\tTX Queue %d rings\n", queue); |
| |
| if (priv->extend_desc) |
| head_tx = (void *)tx_q->dma_etx; |
| else |
| head_tx = (void *)tx_q->dma_tx; |
| |
| priv->hw->desc->display_ring(head_tx, DMA_TX_SIZE, false); |
| } |
| } |
| |
| static void stmmac_display_rings(struct stmmac_priv *priv) |
| { |
| /* Display RX ring */ |
| stmmac_display_rx_rings(priv); |
| |
| /* Display TX ring */ |
| stmmac_display_tx_rings(priv); |
| } |
| |
| static int stmmac_set_bfsize(int mtu, int bufsize) |
| { |
| int ret = bufsize; |
| |
| if (mtu >= BUF_SIZE_4KiB) |
| ret = BUF_SIZE_8KiB; |
| else if (mtu >= BUF_SIZE_2KiB) |
| ret = BUF_SIZE_4KiB; |
| else if (mtu > DEFAULT_BUFSIZE) |
| ret = BUF_SIZE_2KiB; |
| else |
| ret = DEFAULT_BUFSIZE; |
| |
| return ret; |
| } |
| |
| /** |
| * stmmac_clear_rx_descriptors - clear RX descriptors |
| * @priv: driver private structure |
| * @queue: RX queue index |
| * Description: this function is called to clear the RX descriptors |
| * in case of both basic and extended descriptors are used. |
| */ |
| static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) |
| { |
| struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; |
| int i; |
| |
| /* Clear the RX descriptors */ |
| for (i = 0; i < DMA_RX_SIZE; i++) |
| if (priv->extend_desc) |
| priv->hw->desc->init_rx_desc(&rx_q->dma_erx[i].basic, |
| priv->use_riwt, priv->mode, |
| (i == DMA_RX_SIZE - 1)); |
| else |
| priv->hw->desc->init_rx_desc(&rx_q->dma_rx[i], |
| priv->use_riwt, priv->mode, |
| (i == DMA_RX_SIZE - 1)); |
| } |
| |
| /** |
| * stmmac_clear_tx_descriptors - clear tx descriptors |
| * @priv: driver private structure |
| * @queue: TX queue index. |
| * Description: this function is called to clear the TX descriptors |
| * in case of both basic and extended descriptors are used. |
| */ |
| static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) |
| { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; |
| int i; |
| |
| /* Clear the TX descriptors */ |
| for (i = 0; i < DMA_TX_SIZE; i++) |
| if (priv->extend_desc) |
| priv->hw->desc->init_tx_desc(&tx_q->dma_etx[i].basic, |
| priv->mode, |
| (i == DMA_TX_SIZE - 1)); |
| else |
| priv->hw->desc->init_tx_desc(&tx_q->dma_tx[i], |
| priv->mode, |
| (i == DMA_TX_SIZE - 1)); |
| } |
| |
| /** |
| * stmmac_clear_descriptors - clear descriptors |
| * @priv: driver private structure |
| * Description: this function is called to clear the TX and RX descriptors |
| * in case of both basic and extended descriptors are used. |
| */ |
| static void stmmac_clear_descriptors(struct stmmac_priv *priv) |
| { |
| u32 rx_queue_cnt = priv->plat->rx_queues_to_use; |
| u32 tx_queue_cnt = priv->plat->tx_queues_to_use; |
| u32 queue; |
| |
| /* Clear the RX descriptors */ |
| for (queue = 0; queue < rx_queue_cnt; queue++) |
| stmmac_clear_rx_descriptors(priv, queue); |
| |
| /* Clear the TX descriptors */ |
| for (queue = 0; queue < tx_queue_cnt; queue++) |
| stmmac_clear_tx_descriptors(priv, queue); |
| } |
| |
| /** |
| * stmmac_init_rx_buffers - init the RX descriptor buffer. |
| * @priv: driver private structure |
| * @p: descriptor pointer |
| * @i: descriptor index |
| * @flags: gfp flag |
| * @queue: RX queue index |
| * Description: this function is called to allocate a receive buffer, perform |
| * the DMA mapping and init the descriptor. |
| */ |
| static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, |
| int i, gfp_t flags, u32 queue) |
| { |
| struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; |
| struct sk_buff *skb; |
| |
| skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags); |
| if (!skb) { |
| netdev_err(priv->dev, |
| "%s: Rx init fails; skb is NULL\n", __func__); |
| return -ENOMEM; |
| } |
| rx_q->rx_skbuff[i] = skb; |
| rx_q->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, |
| priv->dma_buf_sz, |
| DMA_FROM_DEVICE); |
| if (dma_mapping_error(priv->device, rx_q->rx_skbuff_dma[i])) { |
| netdev_err(priv->dev, "%s: DMA mapping error\n", __func__); |
| dev_kfree_skb_any(skb); |
| return -EINVAL; |
| } |
| |
| if (priv->synopsys_id >= DWMAC_CORE_4_00) |
| p->des0 = cpu_to_le32(rx_q->rx_skbuff_dma[i]); |
| else |
| p->des2 = cpu_to_le32(rx_q->rx_skbuff_dma[i]); |
| |
| if ((priv->hw->mode->init_desc3) && |
| (priv->dma_buf_sz == BUF_SIZE_16KiB)) |
| priv->hw->mode->init_desc3(p); |
| |
| return 0; |
| } |
| |
| /** |
| * stmmac_free_rx_buffer - free RX dma buffers |
| * @priv: private structure |
| * @queue: RX queue index |
| * @i: buffer index. |
| */ |
| static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) |
| { |
| struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; |
| |
| if (rx_q->rx_skbuff[i]) { |
| dma_unmap_single(priv->device, rx_q->rx_skbuff_dma[i], |
| priv->dma_buf_sz, DMA_FROM_DEVICE); |
| dev_kfree_skb_any(rx_q->rx_skbuff[i]); |
| } |
| rx_q->rx_skbuff[i] = NULL; |
| } |
| |
| /** |
| * stmmac_free_tx_buffer - free RX dma buffers |
| * @priv: private structure |
| * @queue: RX queue index |
| * @i: buffer index. |
| */ |
| static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) |
| { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; |
| |
| if (tx_q->tx_skbuff_dma[i].buf) { |
| if (tx_q->tx_skbuff_dma[i].map_as_page) |
| dma_unmap_page(priv->device, |
| tx_q->tx_skbuff_dma[i].buf, |
| tx_q->tx_skbuff_dma[i].len, |
| DMA_TO_DEVICE); |
| else |
| dma_unmap_single(priv->device, |
| tx_q->tx_skbuff_dma[i].buf, |
| tx_q->tx_skbuff_dma[i].len, |
| DMA_TO_DEVICE); |
| } |
| |
| if (tx_q->tx_skbuff[i]) { |
| dev_kfree_skb_any(tx_q->tx_skbuff[i]); |
| tx_q->tx_skbuff[i] = NULL; |
| tx_q->tx_skbuff_dma[i].buf = 0; |
| tx_q->tx_skbuff_dma[i].map_as_page = false; |
| } |
| } |
| |
| /** |
| * init_dma_rx_desc_rings - init the RX descriptor rings |
| * @dev: net device structure |
| * @flags: gfp flag. |
| * Description: this function initializes the DMA RX descriptors |
| * and allocates the socket buffers. It supports the chained and ring |
| * modes. |
| */ |
| static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) |
| { |
| struct stmmac_priv *priv = netdev_priv(dev); |
| u32 rx_count = priv->plat->rx_queues_to_use; |
| unsigned int bfsize = 0; |
| int ret = -ENOMEM; |
| u32 queue; |
| int i; |
| |
| if (priv->hw->mode->set_16kib_bfsize) |
| bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu); |
| |
| if (bfsize < BUF_SIZE_16KiB) |
| bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); |
| |
| priv->dma_buf_sz = bfsize; |
| |
| /* RX INITIALIZATION */ |
| netif_dbg(priv, probe, priv->dev, |
| "SKB addresses:\nskb\t\tskb data\tdma data\n"); |
| |
| for (queue = 0; queue < rx_count; queue++) { |
| struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; |
| |
| netif_dbg(priv, probe, priv->dev, |
| "(%s) dma_rx_phy=0x%08x\n", __func__, |
| (u32)rx_q->dma_rx_phy); |
| |
| for (i = 0; i < DMA_RX_SIZE; i++) { |
| struct dma_desc *p; |
| |
| if (priv->extend_desc) |
| p = &((rx_q->dma_erx + i)->basic); |
| else |
| p = rx_q->dma_rx + i; |
| |
| ret = stmmac_init_rx_buffers(priv, p, i, flags, |
| queue); |
| if (ret) |
| goto err_init_rx_buffers; |
| |
| netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n", |
| rx_q->rx_skbuff[i], rx_q->rx_skbuff[i]->data, |
| (unsigned int)rx_q->rx_skbuff_dma[i]); |
| } |
| |
| rx_q->cur_rx = 0; |
| rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE); |
| |
| stmmac_clear_rx_descriptors(priv, queue); |
| |
| /* Setup the chained descriptor addresses */ |
| if (priv->mode == STMMAC_CHAIN_MODE) { |
| if (priv->extend_desc) |
| priv->hw->mode->init(rx_q->dma_erx, |
| rx_q->dma_rx_phy, |
| DMA_RX_SIZE, 1); |
| else |
| priv->hw->mode->init(rx_q->dma_rx, |
| rx_q->dma_rx_phy, |
| DMA_RX_SIZE, 0); |
| } |
| } |
| |
| buf_sz = bfsize; |
| |
| return 0; |
| |
| err_init_rx_buffers: |
| while (queue >= 0) { |
| while (--i >= 0) |
| stmmac_free_rx_buffer(priv, queue, i); |
| |
| if (queue == 0) |
| break; |
| |
| i = DMA_RX_SIZE; |
| queue--; |
| } |
| |
| return ret; |
| } |
| |
| /** |
| * init_dma_tx_desc_rings - init the TX descriptor rings |
| * @dev: net device structure. |
| * Description: this function initializes the DMA TX descriptors |
| * and allocates the socket buffers. It supports the chained and ring |
| * modes. |
| */ |
| static int init_dma_tx_desc_rings(struct net_device *dev) |
| { |
| struct stmmac_priv *priv = netdev_priv(dev); |
| u32 tx_queue_cnt = priv->plat->tx_queues_to_use; |
| u32 queue; |
| int i; |
| |
| for (queue = 0; queue < tx_queue_cnt; queue++) { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; |
| |
| netif_dbg(priv, probe, priv->dev, |
| "(%s) dma_tx_phy=0x%08x\n", __func__, |
| (u32)tx_q->dma_tx_phy); |
| |
| /* Setup the chained descriptor addresses */ |
| if (priv->mode == STMMAC_CHAIN_MODE) { |
| if (priv->extend_desc) |
| priv->hw->mode->init(tx_q->dma_etx, |
| tx_q->dma_tx_phy, |
| DMA_TX_SIZE, 1); |
| else |
| priv->hw->mode->init(tx_q->dma_tx, |
| tx_q->dma_tx_phy, |
| DMA_TX_SIZE, 0); |
| } |
| |
| for (i = 0; i < DMA_TX_SIZE; i++) { |
| struct dma_desc *p; |
| if (priv->extend_desc) |
| p = &((tx_q->dma_etx + i)->basic); |
| else |
| p = tx_q->dma_tx + i; |
| |
| if (priv->synopsys_id >= DWMAC_CORE_4_00) { |
| p->des0 = 0; |
| p->des1 = 0; |
| p->des2 = 0; |
| p->des3 = 0; |
| } else { |
| p->des2 = 0; |
| } |
| |
| tx_q->tx_skbuff_dma[i].buf = 0; |
| tx_q->tx_skbuff_dma[i].map_as_page = false; |
| tx_q->tx_skbuff_dma[i].len = 0; |
| tx_q->tx_skbuff_dma[i].last_segment = false; |
| tx_q->tx_skbuff[i] = NULL; |
| } |
| |
| tx_q->dirty_tx = 0; |
| tx_q->cur_tx = 0; |
| |
| netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); |
| } |
| |
| return 0; |
| } |
| |
| /** |
| * init_dma_desc_rings - init the RX/TX descriptor rings |
| * @dev: net device structure |
| * @flags: gfp flag. |
| * Description: this function initializes the DMA RX/TX descriptors |
| * and allocates the socket buffers. It supports the chained and ring |
| * modes. |
| */ |
| static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) |
| { |
| struct stmmac_priv *priv = netdev_priv(dev); |
| int ret; |
| |
| ret = init_dma_rx_desc_rings(dev, flags); |
| if (ret) |
| return ret; |
| |
| ret = init_dma_tx_desc_rings(dev); |
| |
| stmmac_clear_descriptors(priv); |
| |
| if (netif_msg_hw(priv)) |
| stmmac_display_rings(priv); |
| |
| return ret; |
| } |
| |
| /** |
| * dma_free_rx_skbufs - free RX dma buffers |
| * @priv: private structure |
| * @queue: RX queue index |
| */ |
| static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) |
| { |
| int i; |
| |
| for (i = 0; i < DMA_RX_SIZE; i++) |
| stmmac_free_rx_buffer(priv, queue, i); |
| } |
| |
| /** |
| * dma_free_tx_skbufs - free TX dma buffers |
| * @priv: private structure |
| * @queue: TX queue index |
| */ |
| static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) |
| { |
| int i; |
| |
| for (i = 0; i < DMA_TX_SIZE; i++) |
| stmmac_free_tx_buffer(priv, queue, i); |
| } |
| |
| /** |
| * free_dma_rx_desc_resources - free RX dma desc resources |
| * @priv: private structure |
| */ |
| static void free_dma_rx_desc_resources(struct stmmac_priv *priv) |
| { |
| u32 rx_count = priv->plat->rx_queues_to_use; |
| u32 queue; |
| |
| /* Free RX queue resources */ |
| for (queue = 0; queue < rx_count; queue++) { |
| struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; |
| |
| /* Release the DMA RX socket buffers */ |
| dma_free_rx_skbufs(priv, queue); |
| |
| /* Free DMA regions of consistent memory previously allocated */ |
| if (!priv->extend_desc) |
| dma_free_coherent(priv->device, |
| DMA_RX_SIZE * sizeof(struct dma_desc), |
| rx_q->dma_rx, rx_q->dma_rx_phy); |
| else |
| dma_free_coherent(priv->device, DMA_RX_SIZE * |
| sizeof(struct dma_extended_desc), |
| rx_q->dma_erx, rx_q->dma_rx_phy); |
| |
| kfree(rx_q->rx_skbuff_dma); |
| kfree(rx_q->rx_skbuff); |
| } |
| } |
| |
| /** |
| * free_dma_tx_desc_resources - free TX dma desc resources |
| * @priv: private structure |
| */ |
| static void free_dma_tx_desc_resources(struct stmmac_priv *priv) |
| { |
| u32 tx_count = priv->plat->tx_queues_to_use; |
| u32 queue = 0; |
| |
| /* Free TX queue resources */ |
| for (queue = 0; queue < tx_count; queue++) { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; |
| |
| /* Release the DMA TX socket buffers */ |
| dma_free_tx_skbufs(priv, queue); |
| |
| /* Free DMA regions of consistent memory previously allocated */ |
| if (!priv->extend_desc) |
| dma_free_coherent(priv->device, |
| DMA_TX_SIZE * sizeof(struct dma_desc), |
| tx_q->dma_tx, tx_q->dma_tx_phy); |
| else |
| dma_free_coherent(priv->device, DMA_TX_SIZE * |
| sizeof(struct dma_extended_desc), |
| tx_q->dma_etx, tx_q->dma_tx_phy); |
| |
| kfree(tx_q->tx_skbuff_dma); |
| kfree(tx_q->tx_skbuff); |
| } |
| } |
| |
| /** |
| * alloc_dma_rx_desc_resources - alloc RX resources. |
| * @priv: private structure |
| * Description: according to which descriptor can be used (extend or basic) |
| * this function allocates the resources for TX and RX paths. In case of |
| * reception, for example, it pre-allocated the RX socket buffer in order to |
| * allow zero-copy mechanism. |
| */ |
| static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) |
| { |
| u32 rx_count = priv->plat->rx_queues_to_use; |
| int ret = -ENOMEM; |
| u32 queue; |
| |
| /* RX queues buffers and DMA */ |
| for (queue = 0; queue < rx_count; queue++) { |
| struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; |
| |
| rx_q->queue_index = queue; |
| rx_q->priv_data = priv; |
| |
| rx_q->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, |
| sizeof(dma_addr_t), |
| GFP_KERNEL); |
| if (!rx_q->rx_skbuff_dma) |
| return -ENOMEM; |
| |
| rx_q->rx_skbuff = kmalloc_array(DMA_RX_SIZE, |
| sizeof(struct sk_buff *), |
| GFP_KERNEL); |
| if (!rx_q->rx_skbuff) |
| goto err_dma; |
| |
| if (priv->extend_desc) { |
| rx_q->dma_erx = dma_zalloc_coherent(priv->device, |
| DMA_RX_SIZE * |
| sizeof(struct |
| dma_extended_desc), |
| &rx_q->dma_rx_phy, |
| GFP_KERNEL); |
| if (!rx_q->dma_erx) |
| goto err_dma; |
| |
| } else { |
| rx_q->dma_rx = dma_zalloc_coherent(priv->device, |
| DMA_RX_SIZE * |
| sizeof(struct |
| dma_desc), |
| &rx_q->dma_rx_phy, |
| GFP_KERNEL); |
| if (!rx_q->dma_rx) |
| goto err_dma; |
| } |
| } |
| |
| return 0; |
| |
| err_dma: |
| free_dma_rx_desc_resources(priv); |
| |
| return ret; |
| } |
| |
| /** |
| * alloc_dma_tx_desc_resources - alloc TX resources. |
| * @priv: private structure |
| * Description: according to which descriptor can be used (extend or basic) |
| * this function allocates the resources for TX and RX paths. In case of |
| * reception, for example, it pre-allocated the RX socket buffer in order to |
| * allow zero-copy mechanism. |
| */ |
| static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) |
| { |
| u32 tx_count = priv->plat->tx_queues_to_use; |
| int ret = -ENOMEM; |
| u32 queue; |
| |
| /* TX queues buffers and DMA */ |
| for (queue = 0; queue < tx_count; queue++) { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; |
| |
| tx_q->queue_index = queue; |
| tx_q->priv_data = priv; |
| |
| tx_q->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE, |
| sizeof(*tx_q->tx_skbuff_dma), |
| GFP_KERNEL); |
| if (!tx_q->tx_skbuff_dma) |
| return -ENOMEM; |
| |
| tx_q->tx_skbuff = kmalloc_array(DMA_TX_SIZE, |
| sizeof(struct sk_buff *), |
| GFP_KERNEL); |
| if (!tx_q->tx_skbuff) |
| goto err_dma_buffers; |
| |
| if (priv->extend_desc) { |
| tx_q->dma_etx = dma_zalloc_coherent(priv->device, |
| DMA_TX_SIZE * |
| sizeof(struct |
| dma_extended_desc), |
| &tx_q->dma_tx_phy, |
| GFP_KERNEL); |
| if (!tx_q->dma_etx) |
| goto err_dma_buffers; |
| } else { |
| tx_q->dma_tx = dma_zalloc_coherent(priv->device, |
| DMA_TX_SIZE * |
| sizeof(struct |
| dma_desc), |
| &tx_q->dma_tx_phy, |
| GFP_KERNEL); |
| if (!tx_q->dma_tx) |
| goto err_dma_buffers; |
| } |
| } |
| |
| return 0; |
| |
| err_dma_buffers: |
| free_dma_tx_desc_resources(priv); |
| |
| return ret; |
| } |
| |
| /** |
| * alloc_dma_desc_resources - alloc TX/RX resources. |
| * @priv: private structure |
| * Description: according to which descriptor can be used (extend or basic) |
| * this function allocates the resources for TX and RX paths. In case of |
| * reception, for example, it pre-allocated the RX socket buffer in order to |
| * allow zero-copy mechanism. |
| */ |
| static int alloc_dma_desc_resources(struct stmmac_priv *priv) |
| { |
| /* RX Allocation */ |
| int ret = alloc_dma_rx_desc_resources(priv); |
| |
| if (ret) |
| return ret; |
| |
| ret = alloc_dma_tx_desc_resources(priv); |
| |
| return ret; |
| } |
| |
| /** |
| * free_dma_desc_resources - free dma desc resources |
| * @priv: private structure |
| */ |
| static void free_dma_desc_resources(struct stmmac_priv *priv) |
| { |
| /* Release the DMA RX socket buffers */ |
| free_dma_rx_desc_resources(priv); |
| |
| /* Release the DMA TX socket buffers */ |
| free_dma_tx_desc_resources(priv); |
| } |
| |
| /** |
| * stmmac_mac_enable_rx_queues - Enable MAC rx queues |
| * @priv: driver private structure |
| * Description: It is used for enabling the rx queues in the MAC |
| */ |
| static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) |
| { |
| u32 rx_queues_count = priv->plat->rx_queues_to_use; |
| int queue; |
| u8 mode; |
| |
| for (queue = 0; queue < rx_queues_count; queue++) { |
| mode = priv->plat->rx_queues_cfg[queue].mode_to_use; |
| priv->hw->mac->rx_queue_enable(priv->hw, mode, queue); |
| } |
| } |
| |
| /** |
| * stmmac_start_rx_dma - start RX DMA channel |
| * @priv: driver private structure |
| * @chan: RX channel index |
| * Description: |
| * This starts a RX DMA channel |
| */ |
| static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) |
| { |
| netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); |
| priv->hw->dma->start_rx(priv->ioaddr, chan); |
| } |
| |
| /** |
| * stmmac_start_tx_dma - start TX DMA channel |
| * @priv: driver private structure |
| * @chan: TX channel index |
| * Description: |
| * This starts a TX DMA channel |
| */ |
| static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) |
| { |
| netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); |
| priv->hw->dma->start_tx(priv->ioaddr, chan); |
| } |
| |
| /** |
| * stmmac_stop_rx_dma - stop RX DMA channel |
| * @priv: driver private structure |
| * @chan: RX channel index |
| * Description: |
| * This stops a RX DMA channel |
| */ |
| static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) |
| { |
| netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); |
| priv->hw->dma->stop_rx(priv->ioaddr, chan); |
| } |
| |
| /** |
| * stmmac_stop_tx_dma - stop TX DMA channel |
| * @priv: driver private structure |
| * @chan: TX channel index |
| * Description: |
| * This stops a TX DMA channel |
| */ |
| static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) |
| { |
| netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); |
| priv->hw->dma->stop_tx(priv->ioaddr, chan); |
| } |
| |
| /** |
| * stmmac_start_all_dma - start all RX and TX DMA channels |
| * @priv: driver private structure |
| * Description: |
| * This starts all the RX and TX DMA channels |
| */ |
| static void stmmac_start_all_dma(struct stmmac_priv *priv) |
| { |
| u32 rx_channels_count = priv->plat->rx_queues_to_use; |
| u32 tx_channels_count = priv->plat->tx_queues_to_use; |
| u32 chan = 0; |
| |
| for (chan = 0; chan < rx_channels_count; chan++) |
| stmmac_start_rx_dma(priv, chan); |
| |
| for (chan = 0; chan < tx_channels_count; chan++) |
| stmmac_start_tx_dma(priv, chan); |
| } |
| |
| /** |
| * stmmac_stop_all_dma - stop all RX and TX DMA channels |
| * @priv: driver private structure |
| * Description: |
| * This stops the RX and TX DMA channels |
| */ |
| static void stmmac_stop_all_dma(struct stmmac_priv *priv) |
| { |
| u32 rx_channels_count = priv->plat->rx_queues_to_use; |
| u32 tx_channels_count = priv->plat->tx_queues_to_use; |
| u32 chan = 0; |
| |
| for (chan = 0; chan < rx_channels_count; chan++) |
| stmmac_stop_rx_dma(priv, chan); |
| |
| for (chan = 0; chan < tx_channels_count; chan++) |
| stmmac_stop_tx_dma(priv, chan); |
| } |
| |
| /** |
| * stmmac_dma_operation_mode - HW DMA operation mode |
| * @priv: driver private structure |
| * Description: it is used for configuring the DMA operation mode register in |
| * order to program the tx/rx DMA thresholds or Store-And-Forward mode. |
| */ |
| static void stmmac_dma_operation_mode(struct stmmac_priv *priv) |
| { |
| u32 rx_channels_count = priv->plat->rx_queues_to_use; |
| u32 tx_channels_count = priv->plat->tx_queues_to_use; |
| int rxfifosz = priv->plat->rx_fifo_size; |
| u32 txmode = 0; |
| u32 rxmode = 0; |
| u32 chan = 0; |
| |
| if (rxfifosz == 0) |
| rxfifosz = priv->dma_cap.rx_fifo_size; |
| |
| if (priv->plat->force_thresh_dma_mode) { |
| txmode = tc; |
| rxmode = tc; |
| } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { |
| /* |
| * In case of GMAC, SF mode can be enabled |
| * to perform the TX COE in HW. This depends on: |
| * 1) TX COE if actually supported |
| * 2) There is no bugged Jumbo frame support |
| * that needs to not insert csum in the TDES. |
| */ |
| txmode = SF_DMA_MODE; |
| rxmode = SF_DMA_MODE; |
| priv->xstats.threshold = SF_DMA_MODE; |
| } else { |
| txmode = tc; |
| rxmode = SF_DMA_MODE; |
| } |
| |
| /* configure all channels */ |
| if (priv->synopsys_id >= DWMAC_CORE_4_00) { |
| for (chan = 0; chan < rx_channels_count; chan++) |
| priv->hw->dma->dma_rx_mode(priv->ioaddr, rxmode, chan, |
| rxfifosz); |
| |
| for (chan = 0; chan < tx_channels_count; chan++) |
| priv->hw->dma->dma_tx_mode(priv->ioaddr, txmode, chan); |
| } else { |
| priv->hw->dma->dma_mode(priv->ioaddr, txmode, rxmode, |
| rxfifosz); |
| } |
| } |
| |
| /** |
| * stmmac_tx_clean - to manage the transmission completion |
| * @priv: driver private structure |
| * @queue: TX queue index |
| * Description: it reclaims the transmit resources after transmission completes. |
| */ |
| static void stmmac_tx_clean(struct stmmac_priv *priv, u32 queue) |
| { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; |
| unsigned int bytes_compl = 0, pkts_compl = 0; |
| unsigned int entry = tx_q->dirty_tx; |
| |
| netif_tx_lock(priv->dev); |
| |
| priv->xstats.tx_clean++; |
| |
| while (entry != tx_q->cur_tx) { |
| struct sk_buff *skb = tx_q->tx_skbuff[entry]; |
| struct dma_desc *p; |
| int status; |
| |
| if (priv->extend_desc) |
| p = (struct dma_desc *)(tx_q->dma_etx + entry); |
| else |
| p = tx_q->dma_tx + entry; |
| |
| status = priv->hw->desc->tx_status(&priv->dev->stats, |
| &priv->xstats, p, |
| priv->ioaddr); |
| /* Check if the descriptor is owned by the DMA */ |
| if (unlikely(status & tx_dma_own)) |
| break; |
| |
| /* Just consider the last segment and ...*/ |
| if (likely(!(status & tx_not_ls))) { |
| /* ... verify the status error condition */ |
| if (unlikely(status & tx_err)) { |
| priv->dev->stats.tx_errors++; |
| } else { |
| priv->dev->stats.tx_packets++; |
| priv->xstats.tx_pkt_n++; |
| } |
| stmmac_get_tx_hwtstamp(priv, p, skb); |
| } |
| |
| if (likely(tx_q->tx_skbuff_dma[entry].buf)) { |
| if (tx_q->tx_skbuff_dma[entry].map_as_page) |
| dma_unmap_page(priv->device, |
| tx_q->tx_skbuff_dma[entry].buf, |
| tx_q->tx_skbuff_dma[entry].len, |
| DMA_TO_DEVICE); |
| else |
| dma_unmap_single(priv->device, |
| tx_q->tx_skbuff_dma[entry].buf, |
| tx_q->tx_skbuff_dma[entry].len, |
| DMA_TO_DEVICE); |
| tx_q->tx_skbuff_dma[entry].buf = 0; |
| tx_q->tx_skbuff_dma[entry].len = 0; |
| tx_q->tx_skbuff_dma[entry].map_as_page = false; |
| } |
| |
| if (priv->hw->mode->clean_desc3) |
| priv->hw->mode->clean_desc3(tx_q, p); |
| |
| tx_q->tx_skbuff_dma[entry].last_segment = false; |
| tx_q->tx_skbuff_dma[entry].is_jumbo = false; |
| |
| if (likely(skb != NULL)) { |
| pkts_compl++; |
| bytes_compl += skb->len; |
| dev_consume_skb_any(skb); |
| tx_q->tx_skbuff[entry] = NULL; |
| } |
| |
| priv->hw->desc->release_tx_desc(p, priv->mode); |
| |
| entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); |
| } |
| tx_q->dirty_tx = entry; |
| |
| netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), |
| pkts_compl, bytes_compl); |
| |
| if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, |
| queue))) && |
| stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) { |
| |
| netif_dbg(priv, tx_done, priv->dev, |
| "%s: restart transmit\n", __func__); |
| netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); |
| } |
| |
| if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { |
| stmmac_enable_eee_mode(priv); |
| mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); |
| } |
| netif_tx_unlock(priv->dev); |
| } |
| |
| static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv, u32 chan) |
| { |
| priv->hw->dma->enable_dma_irq(priv->ioaddr, chan); |
| } |
| |
| static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv, u32 chan) |
| { |
| priv->hw->dma->disable_dma_irq(priv->ioaddr, chan); |
| } |
| |
| /** |
| * stmmac_tx_err - to manage the tx error |
| * @priv: driver private structure |
| * @chan: channel index |
| * Description: it cleans the descriptors and restarts the transmission |
| * in case of transmission errors. |
| */ |
| static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) |
| { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; |
| int i; |
| |
| netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); |
| |
| stmmac_stop_tx_dma(priv, chan); |
| dma_free_tx_skbufs(priv, chan); |
| for (i = 0; i < DMA_TX_SIZE; i++) |
| if (priv->extend_desc) |
| priv->hw->desc->init_tx_desc(&tx_q->dma_etx[i].basic, |
| priv->mode, |
| (i == DMA_TX_SIZE - 1)); |
| else |
| priv->hw->desc->init_tx_desc(&tx_q->dma_tx[i], |
| priv->mode, |
| (i == DMA_TX_SIZE - 1)); |
| tx_q->dirty_tx = 0; |
| tx_q->cur_tx = 0; |
| netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); |
| stmmac_start_tx_dma(priv, chan); |
| |
| priv->dev->stats.tx_errors++; |
| netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); |
| } |
| |
| /** |
| * stmmac_set_dma_operation_mode - Set DMA operation mode by channel |
| * @priv: driver private structure |
| * @txmode: TX operating mode |
| * @rxmode: RX operating mode |
| * @chan: channel index |
| * Description: it is used for configuring of the DMA operation mode in |
| * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward |
| * mode. |
| */ |
| static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, |
| u32 rxmode, u32 chan) |
| { |
| int rxfifosz = priv->plat->rx_fifo_size; |
| |
| if (rxfifosz == 0) |
| rxfifosz = priv->dma_cap.rx_fifo_size; |
| |
| if (priv->synopsys_id >= DWMAC_CORE_4_00) { |
| priv->hw->dma->dma_rx_mode(priv->ioaddr, rxmode, chan, |
| rxfifosz); |
| priv->hw->dma->dma_tx_mode(priv->ioaddr, txmode, chan); |
| } else { |
| priv->hw->dma->dma_mode(priv->ioaddr, txmode, rxmode, |
| rxfifosz); |
| } |
| } |
| |
| /** |
| * stmmac_dma_interrupt - DMA ISR |
| * @priv: driver private structure |
| * Description: this is the DMA ISR. It is called by the main ISR. |
| * It calls the dwmac dma routine and schedule poll method in case of some |
| * work can be done. |
| */ |
| static void stmmac_dma_interrupt(struct stmmac_priv *priv) |
| { |
| u32 tx_channel_count = priv->plat->tx_queues_to_use; |
| int status; |
| u32 chan; |
| |
| for (chan = 0; chan < tx_channel_count; chan++) { |
| struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan]; |
| |
| status = priv->hw->dma->dma_interrupt(priv->ioaddr, |
| &priv->xstats, chan); |
| if (likely((status & handle_rx)) || (status & handle_tx)) { |
| if (likely(napi_schedule_prep(&rx_q->napi))) { |
| stmmac_disable_dma_irq(priv, chan); |
| __napi_schedule(&rx_q->napi); |
| } |
| } |
| |
| if (unlikely(status & tx_hard_error_bump_tc)) { |
| /* Try to bump up the dma threshold on this failure */ |
| if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && |
| (tc <= 256)) { |
| tc += 64; |
| if (priv->plat->force_thresh_dma_mode) |
| stmmac_set_dma_operation_mode(priv, |
| tc, |
| tc, |
| chan); |
| else |
| stmmac_set_dma_operation_mode(priv, |
| tc, |
| SF_DMA_MODE, |
| chan); |
| priv->xstats.threshold = tc; |
| } |
| } else if (unlikely(status == tx_hard_error)) { |
| stmmac_tx_err(priv, chan); |
| } |
| } |
| } |
| |
| /** |
| * stmmac_mmc_setup: setup the Mac Management Counters (MMC) |
| * @priv: driver private structure |
| * Description: this masks the MMC irq, in fact, the counters are managed in SW. |
| */ |
| static void stmmac_mmc_setup(struct stmmac_priv *priv) |
| { |
| unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | |
| MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; |
| |
| if (priv->synopsys_id >= DWMAC_CORE_4_00) { |
| priv->ptpaddr = priv->ioaddr + PTP_GMAC4_OFFSET; |
| priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET; |
| } else { |
| priv->ptpaddr = priv->ioaddr + PTP_GMAC3_X_OFFSET; |
| priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET; |
| } |
| |
| dwmac_mmc_intr_all_mask(priv->mmcaddr); |
| |
| if (priv->dma_cap.rmon) { |
| dwmac_mmc_ctrl(priv->mmcaddr, mode); |
| memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); |
| } else |
| netdev_info(priv->dev, "No MAC Management Counters available\n"); |
| } |
| |
| /** |
| * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors |
| * @priv: driver private structure |
| * Description: select the Enhanced/Alternate or Normal descriptors. |
| * In case of Enhanced/Alternate, it checks if the extended descriptors are |
| * supported by the HW capability register. |
| */ |
| static void stmmac_selec_desc_mode(struct stmmac_priv *priv) |
| { |
| if (priv->plat->enh_desc) { |
| dev_info(priv->device, "Enhanced/Alternate descriptors\n"); |
| |
| /* GMAC older than 3.50 has no extended descriptors */ |
| if (priv->synopsys_id >= DWMAC_CORE_3_50) { |
| dev_info(priv->device, "Enabled extended descriptors\n"); |
| priv->extend_desc = 1; |
| } else |
| dev_warn(priv->device, "Extended descriptors not supported\n"); |
| |
| priv->hw->desc = &enh_desc_ops; |
| } else { |
| dev_info(priv->device, "Normal descriptors\n"); |
| priv->hw->desc = &ndesc_ops; |
| } |
| } |
| |
| /** |
| * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. |
| * @priv: driver private structure |
| * Description: |
| * new GMAC chip generations have a new register to indicate the |
| * presence of the optional feature/functions. |
| * This can be also used to override the value passed through the |
| * platform and necessary for old MAC10/100 and GMAC chips. |
| */ |
| static int stmmac_get_hw_features(struct stmmac_priv *priv) |
| { |
| u32 ret = 0; |
| |
| if (priv->hw->dma->get_hw_feature) { |
| priv->hw->dma->get_hw_feature(priv->ioaddr, |
| &priv->dma_cap); |
| ret = 1; |
| } |
| |
| return ret; |
| } |
| |
| /** |
| * stmmac_check_ether_addr - check if the MAC addr is valid |
| * @priv: driver private structure |
| * Description: |
| * it is to verify if the MAC address is valid, in case of failures it |
| * generates a random MAC address |
| */ |
| static void stmmac_check_ether_addr(struct stmmac_priv *priv) |
| { |
| if (!is_valid_ether_addr(priv->dev->dev_addr)) { |
| priv->hw->mac->get_umac_addr(priv->hw, |
| priv->dev->dev_addr, 0); |
| if (!is_valid_ether_addr(priv->dev->dev_addr)) |
| eth_hw_addr_random(priv->dev); |
| netdev_info(priv->dev, "device MAC address %pM\n", |
| priv->dev->dev_addr); |
| } |
| } |
| |
| /** |
| * stmmac_init_dma_engine - DMA init. |
| * @priv: driver private structure |
| * Description: |
| * It inits the DMA invoking the specific MAC/GMAC callback. |
| * Some DMA parameters can be passed from the platform; |
| * in case of these are not passed a default is kept for the MAC or GMAC. |
| */ |
| static int stmmac_init_dma_engine(struct stmmac_priv *priv) |
| { |
| u32 rx_channels_count = priv->plat->rx_queues_to_use; |
| u32 tx_channels_count = priv->plat->tx_queues_to_use; |
| struct stmmac_rx_queue *rx_q; |
| struct stmmac_tx_queue *tx_q; |
| u32 dummy_dma_rx_phy = 0; |
| u32 dummy_dma_tx_phy = 0; |
| u32 chan = 0; |
| int atds = 0; |
| int ret = 0; |
| |
| if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { |
| dev_err(priv->device, "Invalid DMA configuration\n"); |
| return -EINVAL; |
| } |
| |
| if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) |
| atds = 1; |
| |
| ret = priv->hw->dma->reset(priv->ioaddr); |
| if (ret) { |
| dev_err(priv->device, "Failed to reset the dma\n"); |
| return ret; |
| } |
| |
| if (priv->synopsys_id >= DWMAC_CORE_4_00) { |
| /* DMA Configuration */ |
| priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg, |
| dummy_dma_tx_phy, dummy_dma_rx_phy, atds); |
| |
| /* DMA RX Channel Configuration */ |
| for (chan = 0; chan < rx_channels_count; chan++) { |
| rx_q = &priv->rx_queue[chan]; |
| |
| priv->hw->dma->init_rx_chan(priv->ioaddr, |
| priv->plat->dma_cfg, |
| rx_q->dma_rx_phy, chan); |
| |
| rx_q->rx_tail_addr = rx_q->dma_rx_phy + |
| (DMA_RX_SIZE * sizeof(struct dma_desc)); |
| priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, |
| rx_q->rx_tail_addr, |
| chan); |
| } |
| |
| /* DMA TX Channel Configuration */ |
| for (chan = 0; chan < tx_channels_count; chan++) { |
| tx_q = &priv->tx_queue[chan]; |
| |
| priv->hw->dma->init_chan(priv->ioaddr, |
| priv->plat->dma_cfg, |
| chan); |
| |
| priv->hw->dma->init_tx_chan(priv->ioaddr, |
| priv->plat->dma_cfg, |
| tx_q->dma_tx_phy, chan); |
| |
| tx_q->tx_tail_addr = tx_q->dma_tx_phy + |
| (DMA_TX_SIZE * sizeof(struct dma_desc)); |
| priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, |
| tx_q->tx_tail_addr, |
| chan); |
| } |
| } else { |
| rx_q = &priv->rx_queue[chan]; |
| tx_q = &priv->tx_queue[chan]; |
| priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg, |
| tx_q->dma_tx_phy, rx_q->dma_rx_phy, atds); |
| } |
| |
| if (priv->plat->axi && priv->hw->dma->axi) |
| priv->hw->dma->axi(priv->ioaddr, priv->plat->axi); |
| |
| return ret; |
| } |
| |
| /** |
| * stmmac_tx_timer - mitigation sw timer for tx. |
| * @data: data pointer |
| * Description: |
| * This is the timer handler to directly invoke the stmmac_tx_clean. |
| */ |
| static void stmmac_tx_timer(unsigned long data) |
| { |
| struct stmmac_priv *priv = (struct stmmac_priv *)data; |
| u32 tx_queues_count = priv->plat->tx_queues_to_use; |
| u32 queue; |
| |
| /* let's scan all the tx queues */ |
| for (queue = 0; queue < tx_queues_count; queue++) |
| stmmac_tx_clean(priv, queue); |
| } |
| |
| /** |
| * stmmac_init_tx_coalesce - init tx mitigation options. |
| * @priv: driver private structure |
| * Description: |
| * This inits the transmit coalesce parameters: i.e. timer rate, |
| * timer handler and default threshold used for enabling the |
| * interrupt on completion bit. |
| */ |
| static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) |
| { |
| priv->tx_coal_frames = STMMAC_TX_FRAMES; |
| priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; |
| init_timer(&priv->txtimer); |
| priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer); |
| priv->txtimer.data = (unsigned long)priv; |
| priv->txtimer.function = stmmac_tx_timer; |
| add_timer(&priv->txtimer); |
| } |
| |
| static void stmmac_set_rings_length(struct stmmac_priv *priv) |
| { |
| u32 rx_channels_count = priv->plat->rx_queues_to_use; |
| u32 tx_channels_count = priv->plat->tx_queues_to_use; |
| u32 chan; |
| |
| /* set TX ring length */ |
| if (priv->hw->dma->set_tx_ring_len) { |
| for (chan = 0; chan < tx_channels_count; chan++) |
| priv->hw->dma->set_tx_ring_len(priv->ioaddr, |
| (DMA_TX_SIZE - 1), chan); |
| } |
| |
| /* set RX ring length */ |
| if (priv->hw->dma->set_rx_ring_len) { |
| for (chan = 0; chan < rx_channels_count; chan++) |
| priv->hw->dma->set_rx_ring_len(priv->ioaddr, |
| (DMA_RX_SIZE - 1), chan); |
| } |
| } |
| |
| /** |
| * stmmac_set_tx_queue_weight - Set TX queue weight |
| * @priv: driver private structure |
| * Description: It is used for setting TX queues weight |
| */ |
| static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) |
| { |
| u32 tx_queues_count = priv->plat->tx_queues_to_use; |
| u32 weight; |
| u32 queue; |
| |
| for (queue = 0; queue < tx_queues_count; queue++) { |
| weight = priv->plat->tx_queues_cfg[queue].weight; |
| priv->hw->mac->set_mtl_tx_queue_weight(priv->hw, weight, queue); |
| } |
| } |
| |
| /** |
| * stmmac_configure_cbs - Configure CBS in TX queue |
| * @priv: driver private structure |
| * Description: It is used for configuring CBS in AVB TX queues |
| */ |
| static void stmmac_configure_cbs(struct stmmac_priv *priv) |
| { |
| u32 tx_queues_count = priv->plat->tx_queues_to_use; |
| u32 mode_to_use; |
| u32 queue; |
| |
| /* queue 0 is reserved for legacy traffic */ |
| for (queue = 1; queue < tx_queues_count; queue++) { |
| mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; |
| if (mode_to_use == MTL_QUEUE_DCB) |
| continue; |
| |
| priv->hw->mac->config_cbs(priv->hw, |
| priv->plat->tx_queues_cfg[queue].send_slope, |
| priv->plat->tx_queues_cfg[queue].idle_slope, |
| priv->plat->tx_queues_cfg[queue].high_credit, |
| priv->plat->tx_queues_cfg[queue].low_credit, |
| queue); |
| } |
| } |
| |
| /** |
| * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel |
| * @priv: driver private structure |
| * Description: It is used for mapping RX queues to RX dma channels |
| */ |
| static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) |
| { |
| u32 rx_queues_count = priv->plat->rx_queues_to_use; |
| u32 queue; |
| u32 chan; |
| |
| for (queue = 0; queue < rx_queues_count; queue++) { |
| chan = priv->plat->rx_queues_cfg[queue].chan; |
| priv->hw->mac->map_mtl_to_dma(priv->hw, queue, chan); |
| } |
| } |
| |
| /** |
| * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority |
| * @priv: driver private structure |
| * Description: It is used for configuring the RX Queue Priority |
| */ |
| static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) |
| { |
| u32 rx_queues_count = priv->plat->rx_queues_to_use; |
| u32 queue; |
| u32 prio; |
| |
| for (queue = 0; queue < rx_queues_count; queue++) { |
| if (!priv->plat->rx_queues_cfg[queue].use_prio) |
| continue; |
| |
| prio = priv->plat->rx_queues_cfg[queue].prio; |
| priv->hw->mac->rx_queue_prio(priv->hw, prio, queue); |
| } |
| } |
| |
| /** |
| * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority |
| * @priv: driver private structure |
| * Description: It is used for configuring the TX Queue Priority |
| */ |
| static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) |
| { |
| u32 tx_queues_count = priv->plat->tx_queues_to_use; |
| u32 queue; |
| u32 prio; |
| |
| for (queue = 0; queue < tx_queues_count; queue++) { |
| if (!priv->plat->tx_queues_cfg[queue].use_prio) |
| continue; |
| |
| prio = priv->plat->tx_queues_cfg[queue].prio; |
| priv->hw->mac->tx_queue_prio(priv->hw, prio, queue); |
| } |
| } |
| |
| /** |
| * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing |
| * @priv: driver private structure |
| * Description: It is used for configuring the RX queue routing |
| */ |
| static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) |
| { |
| u32 rx_queues_count = priv->plat->rx_queues_to_use; |
| u32 queue; |
| u8 packet; |
| |
| for (queue = 0; queue < rx_queues_count; queue++) { |
| /* no specific packet type routing specified for the queue */ |
| if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) |
| continue; |
| |
| packet = priv->plat->rx_queues_cfg[queue].pkt_route; |
| priv->hw->mac->rx_queue_prio(priv->hw, packet, queue); |
| } |
| } |
| |
| /** |
| * stmmac_mtl_configuration - Configure MTL |
| * @priv: driver private structure |
| * Description: It is used for configurring MTL |
| */ |
| static void stmmac_mtl_configuration(struct stmmac_priv *priv) |
| { |
| u32 rx_queues_count = priv->plat->rx_queues_to_use; |
| u32 tx_queues_count = priv->plat->tx_queues_to_use; |
| |
| if (tx_queues_count > 1 && priv->hw->mac->set_mtl_tx_queue_weight) |
| stmmac_set_tx_queue_weight(priv); |
| |
| /* Configure MTL RX algorithms */ |
| if (rx_queues_count > 1 && priv->hw->mac->prog_mtl_rx_algorithms) |
| priv->hw->mac->prog_mtl_rx_algorithms(priv->hw, |
| priv->plat->rx_sched_algorithm); |
| |
| /* Configure MTL TX algorithms */ |
| if (tx_queues_count > 1 && priv->hw->mac->prog_mtl_tx_algorithms) |
| priv->hw->mac->prog_mtl_tx_algorithms(priv->hw, |
| priv->plat->tx_sched_algorithm); |
| |
| /* Configure CBS in AVB TX queues */ |
| if (tx_queues_count > 1 && priv->hw->mac->config_cbs) |
| stmmac_configure_cbs(priv); |
| |
| /* Map RX MTL to DMA channels */ |
| if (priv->hw->mac->map_mtl_to_dma) |
| stmmac_rx_queue_dma_chan_map(priv); |
| |
| /* Enable MAC RX Queues */ |
| if (priv->hw->mac->rx_queue_enable) |
| stmmac_mac_enable_rx_queues(priv); |
| |
| /* Set RX priorities */ |
| if (rx_queues_count > 1 && priv->hw->mac->rx_queue_prio) |
| stmmac_mac_config_rx_queues_prio(priv); |
| |
| /* Set TX priorities */ |
| if (tx_queues_count > 1 && priv->hw->mac->tx_queue_prio) |
| stmmac_mac_config_tx_queues_prio(priv); |
| |
| /* Set RX routing */ |
| if (rx_queues_count > 1 && priv->hw->mac->rx_queue_routing) |
| stmmac_mac_config_rx_queues_routing(priv); |
| } |
| |
| /** |
| * stmmac_hw_setup - setup mac in a usable state. |
| * @dev : pointer to the device structure. |
| * Description: |
| * this is the main function to setup the HW in a usable state because the |
| * dma engine is reset, the core registers are configured (e.g. AXI, |
| * Checksum features, timers). The DMA is ready to start receiving and |
| * transmitting. |
| * Return value: |
| * 0 on success and an appropriate (-)ve integer as defined in errno.h |
| * file on failure. |
| */ |
| static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) |
| { |
| struct stmmac_priv *priv = netdev_priv(dev); |
| u32 rx_cnt = priv->plat->rx_queues_to_use; |
| u32 tx_cnt = priv->plat->tx_queues_to_use; |
| u32 chan; |
| int ret; |
| |
| /* DMA initialization and SW reset */ |
| ret = stmmac_init_dma_engine(priv); |
| if (ret < 0) { |
| netdev_err(priv->dev, "%s: DMA engine initialization failed\n", |
| __func__); |
| return ret; |
| } |
| |
| /* Copy the MAC addr into the HW */ |
| priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0); |
| |
| /* PS and related bits will be programmed according to the speed */ |
| if (priv->hw->pcs) { |
| int speed = priv->plat->mac_port_sel_speed; |
| |
| if ((speed == SPEED_10) || (speed == SPEED_100) || |
| (speed == SPEED_1000)) { |
| priv->hw->ps = speed; |
| } else { |
| dev_warn(priv->device, "invalid port speed\n"); |
| priv->hw->ps = 0; |
| } |
| } |
| |
| /* Initialize the MAC Core */ |
| priv->hw->mac->core_init(priv->hw, dev->mtu); |
| |
| /* Initialize MTL*/ |
| if (priv->synopsys_id >= DWMAC_CORE_4_00) |
| stmmac_mtl_configuration(priv); |
| |
| ret = priv->hw->mac->rx_ipc(priv->hw); |
| if (!ret) { |
| netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); |
| priv->plat->rx_coe = STMMAC_RX_COE_NONE; |
| priv->hw->rx_csum = 0; |
| } |
| |
| /* Enable the MAC Rx/Tx */ |
| priv->hw->mac->set_mac(priv->ioaddr, true); |
| |
| /* Set the HW DMA mode and the COE */ |
| stmmac_dma_operation_mode(priv); |
| |
| stmmac_mmc_setup(priv); |
| |
| if (init_ptp) { |
| ret = clk_prepare_enable(priv->plat->clk_ptp_ref); |
| if (ret < 0) |
| netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret); |
| |
| ret = stmmac_init_ptp(priv); |
| if (ret == -EOPNOTSUPP) |
| netdev_warn(priv->dev, "PTP not supported by HW\n"); |
| else if (ret) |
| netdev_warn(priv->dev, "PTP init failed\n"); |
| } |
| |
| #ifdef CONFIG_DEBUG_FS |
| ret = stmmac_init_fs(dev); |
| if (ret < 0) |
| netdev_warn(priv->dev, "%s: failed debugFS registration\n", |
| __func__); |
| #endif |
| /* Start the ball rolling... */ |
| stmmac_start_all_dma(priv); |
| |
| priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; |
| |
| if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { |
| priv->rx_riwt = MAX_DMA_RIWT; |
| priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT, rx_cnt); |
| } |
| |
| if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane) |
| priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0); |
| |
| /* set TX and RX rings length */ |
| stmmac_set_rings_length(priv); |
| |
| /* Enable TSO */ |
| if (priv->tso) { |
| for (chan = 0; chan < tx_cnt; chan++) |
| priv->hw->dma->enable_tso(priv->ioaddr, 1, chan); |
| } |
| |
| return 0; |
| } |
| |
| static void stmmac_hw_teardown(struct net_device *dev) |
| { |
| struct stmmac_priv *priv = netdev_priv(dev); |
| |
| clk_disable_unprepare(priv->plat->clk_ptp_ref); |
| } |
| |
| /** |
| * stmmac_open - open entry point of the driver |
| * @dev : pointer to the device structure. |
| * Description: |
| * This function is the open entry point of the driver. |
| * Return value: |
| * 0 on success and an appropriate (-)ve integer as defined in errno.h |
| * file on failure. |
| */ |
| static int stmmac_open(struct net_device *dev) |
| { |
| struct stmmac_priv *priv = netdev_priv(dev); |
| int ret; |
| |
| stmmac_check_ether_addr(priv); |
| |
| if (priv->hw->pcs != STMMAC_PCS_RGMII && |
| priv->hw->pcs != STMMAC_PCS_TBI && |
| priv->hw->pcs != STMMAC_PCS_RTBI) { |
| ret = stmmac_init_phy(dev); |
| if (ret) { |
| netdev_err(priv->dev, |
| "%s: Cannot attach to PHY (error: %d)\n", |
| __func__, ret); |
| return ret; |
| } |
| } |
| |
| /* Extra statistics */ |
| memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); |
| priv->xstats.threshold = tc; |
| |
| priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); |
| priv->rx_copybreak = STMMAC_RX_COPYBREAK; |
| |
| ret = alloc_dma_desc_resources(priv); |
| if (ret < 0) { |
| netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", |
| __func__); |
| goto dma_desc_error; |
| } |
| |
| ret = init_dma_desc_rings(dev, GFP_KERNEL); |
| if (ret < 0) { |
| netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", |
| __func__); |
| goto init_error; |
| } |
| |
| ret = stmmac_hw_setup(dev, true); |
| if (ret < 0) { |
| netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); |
| goto init_error; |
| } |
| |
| stmmac_init_tx_coalesce(priv); |
| |
| if (dev->phydev) |
| phy_start(dev->phydev); |
| |
| /* Request the IRQ lines */ |
| ret = request_irq(dev->irq, stmmac_interrupt, |
| IRQF_SHARED, dev->name, dev); |
| if (unlikely(ret < 0)) { |
| netdev_err(priv->dev, |
| "%s: ERROR: allocating the IRQ %d (error: %d)\n", |
| __func__, dev->irq, ret); |
| goto irq_error; |
| } |
| |
| /* Request the Wake IRQ in case of another line is used for WoL */ |
| if (priv->wol_irq != dev->irq) { |
| ret = request_irq(priv->wol_irq, stmmac_interrupt, |
| IRQF_SHARED, dev->name, dev); |
| if (unlikely(ret < 0)) { |
| netdev_err(priv->dev, |
| "%s: ERROR: allocating the WoL IRQ %d (%d)\n", |
| __func__, priv->wol_irq, ret); |
| goto wolirq_error; |
| } |
| } |
| |
| /* Request the IRQ lines */ |
| if (priv->lpi_irq > 0) { |
| ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, |
| dev->name, dev); |
| if (unlikely(ret < 0)) { |
| netdev_err(priv->dev, |
| "%s: ERROR: allocating the LPI IRQ %d (%d)\n", |
| __func__, priv->lpi_irq, ret); |
| goto lpiirq_error; |
| } |
| } |
| |
| stmmac_enable_all_queues(priv); |
| stmmac_start_all_queues(priv); |
| |
| return 0; |
| |
| lpiirq_error: |
| if (priv->wol_irq != dev->irq) |
| free_irq(priv->wol_irq, dev); |
| wolirq_error: |
| free_irq(dev->irq, dev); |
| irq_error: |
| if (dev->phydev) |
| phy_stop(dev->phydev); |
| |
| del_timer_sync(&priv->txtimer); |
| stmmac_hw_teardown(dev); |
| init_error: |
| free_dma_desc_resources(priv); |
| dma_desc_error: |
| if (dev->phydev) |
| phy_disconnect(dev->phydev); |
| |
| return ret; |
| } |
| |
| /** |
| * stmmac_release - close entry point of the driver |
| * @dev : device pointer. |
| * Description: |
| * This is the stop entry point of the driver. |
| */ |
| static int stmmac_release(struct net_device *dev) |
| { |
| struct stmmac_priv *priv = netdev_priv(dev); |
| |
| if (priv->eee_enabled) |
| del_timer_sync(&priv->eee_ctrl_timer); |
| |
| /* Stop and disconnect the PHY */ |
| if (dev->phydev) { |
| phy_stop(dev->phydev); |
| phy_disconnect(dev->phydev); |
| } |
| |
| stmmac_stop_all_queues(priv); |
| |
| stmmac_disable_all_queues(priv); |
| |
| del_timer_sync(&priv->txtimer); |
| |
| /* Free the IRQ lines */ |
| free_irq(dev->irq, dev); |
| if (priv->wol_irq != dev->irq) |
| free_irq(priv->wol_irq, dev); |
| if (priv->lpi_irq > 0) |
| free_irq(priv->lpi_irq, dev); |
| |
| /* Stop TX/RX DMA and clear the descriptors */ |
| stmmac_stop_all_dma(priv); |
| |
| /* Release and free the Rx/Tx resources */ |
| free_dma_desc_resources(priv); |
| |
| /* Disable the MAC Rx/Tx */ |
| priv->hw->mac->set_mac(priv->ioaddr, false); |
| |
| netif_carrier_off(dev); |
| |
| #ifdef CONFIG_DEBUG_FS |
| stmmac_exit_fs(dev); |
| #endif |
| |
| stmmac_release_ptp(priv); |
| |
| return 0; |
| } |
| |
| /** |
| * stmmac_tso_allocator - close entry point of the driver |
| * @priv: driver private structure |
| * @des: buffer start address |
| * @total_len: total length to fill in descriptors |
| * @last_segmant: condition for the last descriptor |
| * @queue: TX queue index |
| * Description: |
| * This function fills descriptor and request new descriptors according to |
| * buffer length to fill |
| */ |
| static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des, |
| int total_len, bool last_segment, u32 queue) |
| { |
| struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; |
| struct dma_desc *desc; |
| u32 buff_size; |
| int tmp_len; |
| |
| tmp_len = total_len; |
| |
| while (tmp_len > 0) { |
| tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); |
| desc = tx_q->dma_tx + tx_q->cur_tx; |
| |
| desc->des0 = cpu_to_le32(des + (total_len - tmp_len)); |
| buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? |
| TSO_MAX_BUFF_SIZE : tmp_len; |
| |
| priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size, |
| 0, 1, |
| (last_segment) && (buff_size < TSO_MAX_BUFF_SIZE), |
| 0, 0); |
| |
| tmp_len -= TSO_MAX_BUFF_SIZE; |
| } |
| } |
| |
| /** |
| * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) |
| * @skb : the socket buffer |
| * @dev : device pointer |
| * Description: this is the transmit function that is called on TSO frames |
| * (support available on GMAC4 and newer chips). |
| * Diagram below show the ring programming in case of TSO frames: |
| * |
| * First Descriptor |
| * -------- |
| * | DES0 |---> buffer1 = L2/L3/L4 header |
| * | DES1 |---> TCP Payload (can continue on next descr...) |
| * | DES2 |---> buffer 1 and 2 len |
| * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] |
| * -------- |
| * | |
| * ... |
| * | |
| * -------- |
| * | DES0 | --| Split TCP Payload on Buffers 1 and 2 |
| * | DES1 | --| |
| * | DES2 | --> buffer 1 and 2 len |
| * | DES3 | |
| * -------- |
| * |
| * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. |
| */ |
| static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) |
| { |
| struct dma_desc *desc, *first, *mss_desc = NULL; |
| struct stmmac_priv *priv = netdev_priv(dev); |
| int nfrags = skb_shinfo(skb)->nr_frags; |
| u32 queue = skb_get_queue_mapping(skb); |
| unsigned int first_entry, des; |
| struct stmmac_tx_queue *tx_q; |
| int tmp_pay_len = 0; |
| u32 pay_len, mss; |
| u8 proto_hdr_len; |
| int i; |
| |
| tx_q = &priv->tx_queue[queue]; |
| |
| /* Compute header lengths */ |
| proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); |
| |
| /* Desc availability based on threshold should be enough safe */ |
| if (unlikely(stmmac_tx_avail(priv, queue) < |
| (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { |
| if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { |
| netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, |
| queue)); |
| /* This is a hard error, log it. */ |
| netdev_err(priv->dev, |
| "%s: Tx Ring full when queue awake\n", |
| __func__); |
| } |
| return NETDEV_TX_BUSY; |
| } |
| |
| pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ |
| |
| mss = skb_shinfo(skb)->gso_size; |
| |
| /* set new MSS value if needed */ |
| if (mss != priv->mss) { |
| mss_desc = tx_q->dma_tx + tx_q->cur_tx; |
| priv->hw->desc->set_mss(mss_desc, mss); |
| priv->mss = mss; |
| tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); |
| } |
| |
| if (netif_msg_tx_queued(priv)) { |
| pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n", |
| __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss); |
| pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, |
| skb->data_len); |
| } |
| |
| first_entry = tx_q->cur_tx; |
| |
| desc = tx_q->dma_tx + first_entry; |
| first = desc; |
| |
| /* first descriptor: fill Headers on Buf1 */ |
| des = dma_map_single(priv->device, skb->data, skb_headlen(skb), |
| DMA_TO_DEVICE); |
| if (dma_mapping_error(priv->device, des)) |
| goto dma_map_err; |
| |
| tx_q->tx_skbuff_dma[first_entry].buf = des; |
| tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); |
| tx_q->tx_skbuff[first_entry] = skb; |
| |
| first->des0 = cpu_to_le32(des); |
| |
| /* Fill start of payload in buff2 of first descriptor */ |
| if (pay_len) |
| first->des1 = cpu_to_le32(des + proto_hdr_len); |
| |
| /* If needed take extra descriptors to fill the remaining payload */ |
| tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; |
| |
| stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); |
| |
| /* Prepare fragments */ |
| for (i = 0; i < nfrags; i++) { |
| const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
| |
| des = skb_frag_dma_map(priv->device, frag, 0, |
| skb_frag_size(frag), |
| DMA_TO_DEVICE); |
| if (dma_mapping_error(priv->device, des)) |
| goto dma_map_err; |
| |
| stmmac_tso_allocator(priv, des, skb_frag_size(frag), |
| (i == nfrags - 1), queue); |
| |
| tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; |
| tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); |
| tx_q->tx_skbuff[tx_q->cur_tx] = NULL; |
| tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; |
| } |
| |
| tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; |
| |
| tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); |
| |
| if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { |
| netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", |
| __func__); |
| netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); |
| } |
| |
| dev->stats.tx_bytes += skb->len; |
| priv->xstats.tx_tso_frames++; |
| priv->xstats.tx_tso_nfrags += nfrags; |
| |
| /* Manage tx mitigation */ |
| priv->tx_count_frames += nfrags + 1; |
| if (likely(priv->tx_coal_frames > priv->tx_count_frames)) { |
| mod_timer(&priv->txtimer, |
| STMMAC_COAL_TIMER(priv->tx_coal_timer)); |
| } else { |
| priv->tx_count_frames = 0; |
| priv->hw->desc->set_tx_ic(desc); |
| priv->xstats.tx_set_ic_bit++; |
| } |
| |
| if (!priv->hwts_tx_en) |
| skb_tx_timestamp(skb); |
| |
| if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && |
| priv->hwts_tx_en)) { |
| /* declare that device is doing timestamping */ |
| skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
| priv->hw->desc->enable_tx_timestamp(first); |
| } |
| |
| /* Complete the first descriptor before granting the DMA */ |
| priv->hw->desc->prepare_tso_tx_desc(first, 1, |
| proto_hdr_len, |
| pay_len, |
| 1, tx_q->tx_skbuff_dma[first_entry].last_segment, |
| tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len)); |
| |
| /* If context desc is used to change MSS */ |
| if (mss_desc) |
| priv->hw->desc->set_tx_owner(mss_desc); |
| |
| /* The own bit must be the latest setting done when prepare the |
| * descriptor and then barrier is needed to make sure that |
| * all is coherent before granting the DMA engine. |
| */ |
| dma_wmb(); |
| |
| if (netif_msg_pktdata(priv)) { |
| pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", |
| __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, |
| tx_q->cur_tx, first, nfrags); |
| |
| priv->hw->desc->display_ring((void *)tx_q->dma_tx, DMA_TX_SIZE, |
| 0); |
| |
| pr_info(">>> frame to be transmitted: "); |
| print_pkt(skb->data, skb_headlen(skb)); |
| } |
| |
| netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); |
| |
| priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, tx_q->tx_tail_addr, |
| queue); |
| |
| return NETDEV_TX_OK; |
| |
| dma_map_err: |
| dev_err(priv->device, "Tx dma map failed\n"); |
| dev_kfree_skb(skb); |
| priv->dev->stats.tx_dropped++; |
| return NETDEV_TX_OK; |
| } |
| |
| /** |
| * stmmac_xmit - Tx entry point of the driver |
| * @skb : the socket buffer |
| * @dev : device pointer |
| * Description : this is the tx entry point of the driver. |
| * It programs the chain or the ring and supports oversized frames |
| * and SG feature. |
| */ |
| static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) |
| { |
| struct stmmac_priv *priv = netdev_priv(dev); |
| unsigned int nopaged_len = skb_headlen(skb); |
| int i, csum_insertion = 0, is_jumbo = 0; |
| u32 queue = skb_get_queue_mapping(skb); |
| int nfrags = skb_shinfo(skb)->nr_frags; |
| int entry; |
| unsigned int first_entry; |
| struct dma_desc *desc, *first; |
| struct stmmac_tx_queue *tx_q; |
| unsigned int enh_desc; |
| unsigned int des; |
| |
| tx_q = &priv->tx_queue[queue]; |
| |
| /* Manage oversized TCP frames for GMAC4 device */ |
| if (skb_is_gso(skb) && priv->tso) { |
| if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
| return stmmac_tso_xmit(skb, dev); |
| } |
| |
| if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { |
| if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { |
| netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, |
| queue)); |
| /* This is a hard error, log it. */ |
| netdev_err(priv->dev, |
| "%s: Tx Ring full when queue awake\n", |
| __func__); |
| } |
| return NETDEV_TX_BUSY; |
| } |
| |
| if (priv->tx_path_in_lpi_mode) |
| stmmac_disable_eee_mode(priv); |
| |
| entry = tx_q->cur_tx; |
| first_entry = entry; |
| |
| csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); |
| |
| if (likely(priv->extend_desc)) |
| desc = (struct dma_desc *)(tx_q->dma_etx + entry); |
| else |
| desc = tx_q->dma_tx + entry; |
| |
| first = desc; |
| |
| tx_q->tx_skbuff[first_entry] = skb; |
| |
| enh_desc = priv->plat->enh_desc; |
| /* To program the descriptors according to the size of the frame */ |
| if (enh_desc) |
| is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc); |
| |
| if (unlikely(is_jumbo) && likely(priv->synopsys_id < |
| DWMAC_CORE_4_00)) { |
| entry = priv->hw->mode->jumbo_frm(tx_q, skb, csum_insertion); |
| if (unlikely(entry < 0)) |
| goto dma_map_err; |
| } |
| |
| for (i = 0; i < nfrags; i++) { |
| const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
| int len = skb_frag_size(frag); |
| bool last_segment = (i == (nfrags - 1)); |
| |
| entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); |
| |
| if (likely(priv->extend_desc)) |
| desc = (struct dma_desc *)(tx_q->dma_etx + entry); |
| else |
| desc = tx_q->dma_tx + entry; |
| |
| des = skb_frag_dma_map(priv->device, frag, 0, len, |
| DMA_TO_DEVICE); |
| if (dma_mapping_error(priv->device, des)) |
| goto dma_map_err; /* should reuse desc w/o issues */ |
| |
| tx_q->tx_skbuff[entry] = NULL; |
| |
| tx_q->tx_skbuff_dma[entry].buf = des; |
| if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) |
| desc->des0 = cpu_to_le32(des); |
| else |
| desc->des2 = cpu_to_le32(des); |
| |
| tx_q->tx_skbuff_dma[entry].map_as_page = true; |
| tx_q->tx_skbuff_dma[entry].len = len; |
| tx_q->tx_skbuff_dma[entry].last_segment = last_segment; |
| |
| /* Prepare the descriptor and set the own bit too */ |
| priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion, |
| priv->mode, 1, last_segment, |
| skb->len); |
| } |
| |
| entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); |
| |
| tx_q->cur_tx = entry; |
| |
| if (netif_msg_pktdata(priv)) { |
| void *tx_head; |
| |
| netdev_dbg(priv->dev, |
| "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", |
| __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, |
| entry, first, nfrags); |
| |
| if (priv->extend_desc) |
| tx_head = (void *)tx_q->dma_etx; |
| else |
| tx_head = (void *)tx_q->dma_tx; |
| |
| priv->hw->desc->display_ring(tx_head, DMA_TX_SIZE, false); |
| |
| netdev_dbg(priv->dev, ">>> frame to be transmitted: "); |
| print_pkt(skb->data, skb->len); |
| } |
| |
| if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { |
| netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", |
| __func__); |
| netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); |
| } |
| |
| dev->stats.tx_bytes += skb->len; |
| |
| /* According to the coalesce parameter the IC bit for the latest |
| * segment is reset and the timer re-started to clean the tx status. |
| * This approach takes care about the fragments: desc is the first |
| * element in case of no SG. |
| */ |
| priv->tx_count_frames += nfrags + 1; |
| if (likely(priv->tx_coal_frames > priv->tx_count_frames)) { |
| mod_timer(&priv->txtimer, |
| STMMAC_COAL_TIMER(priv->tx_coal_timer)); |
| } else { |
| priv->tx_count_frames = 0; |
| priv->hw->desc->set_tx_ic(desc); |
| priv->xstats.tx_set_ic_bit++; |
| } |
| |
| if (!priv->hwts_tx_en) |
| skb_tx_timestamp(skb); |
| |
| /* Ready to fill the first descriptor and set the OWN bit w/o any |
| * problems because all the descriptors are actually ready to be |
| * passed to the DMA engine. |
| */ |
| if (likely(!is_jumbo)) { |
| |