arm64: dts: rockchip: Make use of HDMI0 PHY PLL on rk3588-evb1
The initial vop2 support for rk3588 in mainline is not able to handle
all display modes supported by connected displays, e.g.
2560x1440-75.00Hz, 2048x1152-60.00Hz, 1024x768-60.00Hz.
Additionally, it doesn't cope with non-integer refresh rates like 59.94,
29.97, 23.98, etc.
Make use of the HDMI0 PHY PLL to support the additional display modes.
Note this requires commit "drm/rockchip: vop2: Improve display modes
handling on rk3588", which needs a rework to be upstreamable.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
index 6208846..ce19bbc 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
@@ -330,6 +330,11 @@ &cpu_l3 {
mem-supply = <&vdd_cpu_lit_mem_s0>;
};
+&display_subsystem {
+ clocks = <&hdptxphy_hdmi0>;
+ clock-names = "hdmi0_phy_pll";
+};
+
&gmac0 {
clock_in_out = "output";
phy-handle = <&rgmii_phy>;
