| From e9a321c6b2ac954a7dbf235f419c255a424a1273 Mon Sep 17 00:00:00 2001 |
| From: Alex Deucher <alexander.deucher@amd.com> |
| Date: Mon, 27 Jan 2014 11:54:44 -0500 |
| Subject: drm/radeon: fix DAC interrupt handling on DCE5+ |
| |
| From: Alex Deucher <alexander.deucher@amd.com> |
| |
| commit e9a321c6b2ac954a7dbf235f419c255a424a1273 upstream. |
| |
| DCE5 and newer hardware only has 1 DAC. Use the correct |
| offset. This may fix display problems on certain board |
| configurations. |
| |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/gpu/drm/radeon/evergreen.c | 4 ++-- |
| drivers/gpu/drm/radeon/si.c | 2 +- |
| drivers/gpu/drm/radeon/sid.h | 2 +- |
| 3 files changed, 4 insertions(+), 4 deletions(-) |
| |
| --- a/drivers/gpu/drm/radeon/evergreen.c |
| +++ b/drivers/gpu/drm/radeon/evergreen.c |
| @@ -4298,8 +4298,8 @@ void evergreen_disable_interrupt_state(s |
| WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); |
| } |
| |
| - /* only one DAC on DCE6 */ |
| - if (!ASIC_IS_DCE6(rdev)) |
| + /* only one DAC on DCE5 */ |
| + if (!ASIC_IS_DCE5(rdev)) |
| WREG32(DACA_AUTODETECT_INT_CONTROL, 0); |
| WREG32(DACB_AUTODETECT_INT_CONTROL, 0); |
| |
| --- a/drivers/gpu/drm/radeon/si.c |
| +++ b/drivers/gpu/drm/radeon/si.c |
| @@ -5566,7 +5566,7 @@ static void si_disable_interrupt_state(s |
| } |
| |
| if (!ASIC_IS_NODCE(rdev)) { |
| - WREG32(DACA_AUTODETECT_INT_CONTROL, 0); |
| + WREG32(DAC_AUTODETECT_INT_CONTROL, 0); |
| |
| tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
| WREG32(DC_HPD1_INT_CONTROL, tmp); |
| --- a/drivers/gpu/drm/radeon/sid.h |
| +++ b/drivers/gpu/drm/radeon/sid.h |
| @@ -815,7 +815,7 @@ |
| # define GRPH_PFLIP_INT_MASK (1 << 0) |
| # define GRPH_PFLIP_INT_TYPE (1 << 8) |
| |
| -#define DACA_AUTODETECT_INT_CONTROL 0x66c8 |
| +#define DAC_AUTODETECT_INT_CONTROL 0x67c8 |
| |
| #define DC_HPD1_INT_STATUS 0x601c |
| #define DC_HPD2_INT_STATUS 0x6028 |
