| From e323d56eb06b266b77c2b430cb5f1977ba549e03 Mon Sep 17 00:00:00 2001 |
| From: Krzysztof Kozlowski <k.kozlowski@samsung.com> |
| Date: Fri, 12 Jun 2015 10:53:25 +0900 |
| Subject: clk: exynos4: Fix wrong clock for Exynos4x12 ADC |
| |
| From: Krzysztof Kozlowski <k.kozlowski@samsung.com> |
| |
| commit e323d56eb06b266b77c2b430cb5f1977ba549e03 upstream. |
| |
| The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver. |
| However TSADC is present only on Exynos4210 so on Trats2 board (with |
| Exynos4412 SoC) the exynos-adc driver could not be probed: |
| ERROR: could not get clock /adc@126C0000:adc(0) |
| exynos-adc 126c0000.adc: failed getting clock, err = -2 |
| exynos-adc: probe of 126c0000.adc failed with error -2 |
| |
| Instead on Exynos4x12 SoCs the main clock used by Analog to Digital |
| Converter is located in different register and it is named in datasheet |
| as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock |
| is the same as purpose of TSADC from Exynos4210. |
| |
| The patch adds gate clock for Exynos4x12 using the proper register so |
| backward compatibility is preserved. This fixes the probe of exynos-adc |
| driver on Exynos4x12 boards and allows accessing sensors connected to it |
| on Trats2 board (ntc,ncp15wb473 AP and battery thermistors). |
| |
| Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> |
| Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12") |
| Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> |
| Acked-by: Tomasz Figa <tomasz.figa@gmail.com> |
| Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/clk/samsung/clk-exynos4.c | 2 ++ |
| 1 file changed, 2 insertions(+) |
| |
| --- a/drivers/clk/samsung/clk-exynos4.c |
| +++ b/drivers/clk/samsung/clk-exynos4.c |
| @@ -86,6 +86,7 @@ |
| #define DIV_PERIL4 0xc560 |
| #define DIV_PERIL5 0xc564 |
| #define E4X12_DIV_CAM1 0xc568 |
| +#define E4X12_GATE_BUS_FSYS1 0xc744 |
| #define GATE_SCLK_CAM 0xc820 |
| #define GATE_IP_CAM 0xc920 |
| #define GATE_IP_TV 0xc924 |
| @@ -1097,6 +1098,7 @@ static struct samsung_gate_clock exynos4 |
| 0), |
| GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0, |
| 0), |
| + GATE(CLK_TSADC, "tsadc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, 0), |
| GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), |
| GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), |
| GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, |
