blob: 8e40d774bddd7426fe4ca4761159e15b9b086291 [file] [log] [blame]
From 92597f97a40bf661bebceb92e26ff87c76d562d4 Mon Sep 17 00:00:00 2001
From: "Rafael J. Wysocki" <>
Date: Thu, 31 Mar 2022 19:38:51 +0200
Subject: PCI/PM: Avoid putting Elo i2 PCIe Ports in D3cold
From: Rafael J. Wysocki <>
commit 92597f97a40bf661bebceb92e26ff87c76d562d4 upstream.
If a Root Port on Elo i2 is put into D3cold and then back into D0, the
downstream device becomes permanently inaccessible, so add a bridge D3 DMI
quirk for that system.
This was exposed by 14858dcc3b35 ("PCI: Use pci_update_current_state() in
pci_enable_device_flags()"), but before that commit the Root Port in
question had never been put into D3cold for real due to a mismatch between
its power state retrieved from the PCI_PM_CTRL register (which was
accessible even though the platform firmware indicated that the port was in
D3cold) and the state of an ACPI power resource involved in its power
Reported-by: Stefan Gottwald <>
Signed-off-by: Rafael J. Wysocki <>
Signed-off-by: Bjorn Helgaas <>
Cc: # v5.15+
Signed-off-by: Greg Kroah-Hartman <>
drivers/pci/pci.c | 10 ++++++++++
1 file changed, 10 insertions(+)
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -2517,6 +2517,16 @@ static const struct dmi_system_id bridge
DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
+ /*
+ * Downstream device is not accessible after putting a root port
+ * into D3cold and back into D0 on Elo i2.
+ */
+ .ident = "Elo i2",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Elo Touch Solutions"),
+ },
{ }