Perf events changes for this cycle were:

Platform PMU changes:
=====================

 - x86/intel:
    - Add new Intel Alder Lake and Raptor Lake support

 - x86/amd:
    - AMD Zen4 IBS extensions support
    - Add AMD PerfMonV2 support
    - Add AMD Fam19h Branch Sampling support

Generic changes:
================

 - signal: Deliver SIGTRAP on perf event asynchronously if blocked

   Perf instrumentation can be driven via SIGTRAP, but this causes a problem
   when SIGTRAP is blocked by a task & terminate the task.

   Allow user-space to request these signals asynchronously (after they get
   unblocked) & also give the information to the signal handler when this
   happens:

     " To give user space the ability to clearly distinguish synchronous from
       asynchronous signals, introduce siginfo_t::si_perf_flags and
       TRAP_PERF_FLAG_ASYNC (opted for flags in case more binary information is
       required in future).

       The resolution to the problem is then to (a) no longer force the signal
       (avoiding the terminations), but (b) tell user space via si_perf_flags
       if the signal was synchronous or not, so that such signals can be
       handled differently (e.g. let user space decide to ignore or consider
       the data imprecise). "

 - Unify/standardize the /sys/devices/cpu/events/* output format.

 - Misc fixes & cleanups.

Signed-off-by: Ingo Molnar <mingo@kernel.org>
perf/x86/amd/core: Fix reloading events for SVM

Commit 1018faa6cf23 ("perf/x86/kvm: Fix Host-Only/Guest-Only
counting with SVM disabled") addresses an issue in which the
Host-Only bit in the counter control registers needs to be
masked off when SVM is not enabled.

The events need to be reloaded whenever SVM is enabled or
disabled for a CPU and this requires the PERF_CTL registers
to be reprogrammed using {enable,disable}_all(). However,
PerfMonV2 variants of these functions do not reprogram the
PERF_CTL registers. Hence, the legacy enable_all() function
should also be called.

Fixes: 9622e67e3980 ("perf/x86/amd/core: Add PerfMonV2 counter control")
Reported-by: Like Xu <likexu@tencent.com>
Signed-off-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20220518084327.464005-1-sandipan.das@amd.com
1 file changed