)]}'
{
  "commit": "b844ad301b7504b852dc9c3b10f2da188145e05c",
  "tree": "b76f40423150f0f371d9efe33cc2954047ab17ff",
  "parents": [
    "fe4a2bb801bd5f5e355e3416896d08637058d82c"
  ],
  "author": {
    "name": "Karol Kolacinski",
    "email": "karol.kolacinski@intel.com",
    "time": "Thu May 07 15:51:08 2026 +0200"
  },
  "committer": {
    "name": "Tony Nguyen",
    "email": "anthony.l.nguyen@intel.com",
    "time": "Mon May 11 15:53:19 2026 -0700"
  },
  "message": "ice: support SBQ posted writes with non-posted support for CGU\n\nSideband queue (SBQ) is a HW queue with very short completion time. All\nSBQ writes were posted by default, which means that the driver did not\nhave to wait for completion from the neighbor device, because there was\nnone. This introduced unnecessary delays, where only those delays were\n\"ensuring\" that the command is \"completed\" and this was a potential race\ncondition.\n\nAdd the possibility to perform non-posted writes where it\u0027s necessary to\nwait for completion, instead of relying on fake completion from the FW,\nwhere only the delays are guarding the writes.\n\nFlush the SBQ by reading address 0 from the PHY 0 before issuing SYNC\ncommand to ensure that writes to all PHYs were completed and skip SBQ\nmessage completion if it\u0027s posted.\n\nTo analyze if delays are gone, look for and compare time spent in\nice_sq_send_cmd — posted writes should return immediately after the wr32.\nThat can be done for example by adjusting phc time with phc_ctl on E830\ndevice, for less than 2 seconds to use this new mechanism. Without it,\ncommand below will fail.\n\nReproduction steps:\nphc_ctl eth13 adj 1\nphc_ctl[4478170.994]: adjusted clock by 1.000000 seconds\n\nCheck trace for timing for comparisions:\necho ice_sbq_send_cmd \u003e /sys/kernel/debug/tracing/set_ftrace_filter\necho function_graph \u003e /sys/kernel/debug/tracing/current_tracer\ncat /sys/kernel/debug/tracing/trace\n\nTested on:\n  - Intel E830 NIC (FW version 1.00)\n  - Kernel 6.19.0+\n\nFixes: 8f5ee3c477a8 (\"ice: add support for sideband messages\")\nSigned-off-by: Karol Kolacinski \u003ckarol.kolacinski@intel.com\u003e\nSigned-off-by: Przemyslaw Korba \u003cprzemyslaw.korba@intel.com\u003e\nReviewed-by: Aleksandr Loktionov \u003caleksandr.loktionov@intel.com\u003e\nReviewed-by: Arkadiusz Kubalewski \u003carkadiusz.kubalewski@intel.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0ec65007d6725f5bf8450fc6164956b15e5562d4",
      "old_mode": 33188,
      "old_path": "drivers/net/ethernet/intel/ice/ice_common.c",
      "new_id": "d5007f6c9d6e960807252bcd0d2f353aca45222d",
      "new_mode": 33188,
      "new_path": "drivers/net/ethernet/intel/ice/ice_common.c"
    },
    {
      "type": "modify",
      "old_id": "dcb837cadd182508216d1f18c7449b38f91edab3",
      "old_mode": 33188,
      "old_path": "drivers/net/ethernet/intel/ice/ice_controlq.c",
      "new_id": "a6008dc77fa438145bfa4e8338999e5be182a76c",
      "new_mode": 33188,
      "new_path": "drivers/net/ethernet/intel/ice/ice_controlq.c"
    },
    {
      "type": "modify",
      "old_id": "788040dd662e231cb85ad7da699586b3d5b41160",
      "old_mode": 33188,
      "old_path": "drivers/net/ethernet/intel/ice/ice_controlq.h",
      "new_id": "c50d6fcbacba5635463459bf2db5609de2861640",
      "new_mode": 33188,
      "new_path": "drivers/net/ethernet/intel/ice/ice_controlq.h"
    },
    {
      "type": "modify",
      "old_id": "2c18e16fe053e020a54d7ec6d340432aa517aa8d",
      "old_mode": 33188,
      "old_path": "drivers/net/ethernet/intel/ice/ice_ptp_hw.c",
      "new_id": "5a1a1f5ea9bb021089f20eedd83f1f65f4650e72",
      "new_mode": 33188,
      "new_path": "drivers/net/ethernet/intel/ice/ice_ptp_hw.c"
    },
    {
      "type": "modify",
      "old_id": "21bb861febbfa76e68de653700768ebc89e73a8d",
      "old_mode": 33188,
      "old_path": "drivers/net/ethernet/intel/ice/ice_sbq_cmd.h",
      "new_id": "86a143ebf089f23a530dc2ab7b5acb5f146a659b",
      "new_mode": 33188,
      "new_path": "drivers/net/ethernet/intel/ice/ice_sbq_cmd.h"
    }
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}